Bruno Cardoso Lopes 8e702bba63 Change all checks regarding the presence of any SSE level to always ... take into consideration the presence of AVX. This change, together with the SSEDomainFix enabled for AVX, makes AVX codegen to always (hopefully) emit the same code as SSE for 128-bit vector ops. I don't have a testcase for this, but AVX now beats SSE in performance for 128-bit ops in the majority of programas in the llvm testsuite llvm-svn: 139817		2011-09-15 18:27:36 +00:00
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Alpha	Remove ancient debug info constructs from test cases, they are not relevant to test case's main objective.	2011-09-14 00:29:50 +00:00
ARM	Fix mistake in test runline.	2011-09-12 17:32:58 +00:00
Blackfin	more tests not making the jump into the brave new world.	2011-07-09 16:57:10 +00:00
CBackend	Revert r137134. It breaks some code as Eli pointed out.	2011-08-09 18:56:35 +00:00
CellSPU	Pass signed (not unsigned) 10 bit field to SPU 'ori' instruction.	2011-09-02 10:05:01 +00:00
CPP	manually upgrade a bunch of tests to modern syntax, and remove some that	2011-06-17 03:14:27 +00:00
Generic	This test is already covered by llvm/trunk/test/CodeGen/X86/vsel.ll	2011-09-08 08:43:23 +00:00
MBlaze	Add scheduling information for the MBlaze backend.	2011-04-11 22:31:52 +00:00
Mips	Delete test cases that generate code for allegrex/psp and cannot be repurposed.	2011-09-13 22:29:13 +00:00
MSP430	Fix register-dependent test in MSP430.	2011-05-04 01:01:39 +00:00
PowerPC	Remove ancient debug info constructs from test cases, they are not relevant to test case's main objective.	2011-09-14 00:29:50 +00:00
PTX	PTX: Add initial support for device function calls	2011-08-09 17:36:31 +00:00
SPARC	make the asmparser reject function and type redefinitions. 'Merging' hasn't been	2011-06-17 07:06:44 +00:00
SystemZ	manually upgrade a bunch of tests to modern syntax, and remove some that	2011-06-17 03:14:27 +00:00
Thumb	Disable these tests harder. They're XFAIL'd, but that means they still run, and	2011-09-06 22:08:18 +00:00
Thumb2	Generalize this test's CHECK statements to handle different indvars modes.	2011-09-13 02:46:27 +00:00
X86	Change all checks regarding the presence of any SSE level to always	2011-09-15 18:27:36 +00:00
XCore	Associate a MemOperand with LDWCP nodes introduced during ISel.	2011-09-12 14:43:23 +00:00