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cdae83c48c
Re-comitting with a change that avoids undefined uses getting put into the VRegUses list. The new algorithm remembers the uses encountered while walking backwards until a matching def is found. Contrary to the previous version this: - Works without LiveIntervals being available - Allows to increase the precision to subregisters/lanemasks (not used for now) The changes in the AMDGPU tests are necessary because the R600 scheduler is not stable with respect to the order of nodes in the ready queues. Differential Revision: http://reviews.llvm.org/D9068 llvm-svn: 254683
65 lines
1.9 KiB
LLVM
65 lines
1.9 KiB
LLVM
; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s
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; Test using an integer literal constant.
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; Generated ASM should be:
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; ADD_INT KC0[2].Z literal.x, 5
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; or
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; ADD_INT literal.x KC0[2].Z, 5
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; CHECK: {{^}}i32_literal:
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; CHECK: LSHR
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; CHECK-NEXT: ADD_INT * {{\** *}}T{{[0-9]\.[XYZW]}}, KC0[2].Z, literal.y
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; CHECK-NEXT: 5
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define void @i32_literal(i32 addrspace(1)* %out, i32 %in) {
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entry:
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%0 = add i32 5, %in
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store i32 %0, i32 addrspace(1)* %out
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ret void
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}
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; Test using a float literal constant.
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; Generated ASM should be:
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; ADD KC0[2].Z literal.x, 5.0
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; or
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; ADD literal.x KC0[2].Z, 5.0
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; CHECK: {{^}}float_literal:
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; CHECK: LSHR
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; CHECK-NEXT: ADD * {{\** *}}T{{[0-9]\.[XYZW]}}, KC0[2].Z, literal.y
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; CHECK-NEXT: 1084227584(5.0
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define void @float_literal(float addrspace(1)* %out, float %in) {
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entry:
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%0 = fadd float 5.0, %in
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store float %0, float addrspace(1)* %out
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ret void
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}
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; Make sure inline literals are folded into REG_SEQUENCE instructions.
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; CHECK: {{^}}inline_literal_reg_sequence:
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; CHECK: MOV {{\** *}}T[[GPR:[0-9]]].X, 0.0
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; CHECK-NEXT: MOV {{\** *}}T[[GPR]].Y, 0.0
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; CHECK-NEXT: MOV {{\** *}}T[[GPR]].Z, 0.0
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; CHECK-NEXT: MOV {{\** *}}T[[GPR]].W, 0.0
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define void @inline_literal_reg_sequence(<4 x i32> addrspace(1)* %out) {
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entry:
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store <4 x i32> <i32 0, i32 0, i32 0, i32 0>, <4 x i32> addrspace(1)* %out
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ret void
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}
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; CHECK: {{^}}inline_literal_dot4:
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; CHECK: DOT4 T[[GPR:[0-9]]].X, 1.0
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; CHECK-NEXT: DOT4 T[[GPR]].Y (MASKED), 1.0
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; CHECK-NEXT: DOT4 T[[GPR]].Z (MASKED), 1.0
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; CHECK-NEXT: DOT4 * T[[GPR]].W (MASKED), 1.0
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define void @inline_literal_dot4(float addrspace(1)* %out) {
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entry:
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%0 = call float @llvm.AMDGPU.dp4(<4 x float> <float 1.0, float 1.0, float 1.0, float 1.0>, <4 x float> <float 1.0, float 1.0, float 1.0, float 1.0>)
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store float %0, float addrspace(1)* %out
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ret void
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}
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declare float @llvm.AMDGPU.dp4(<4 x float>, <4 x float>) #1
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attributes #1 = { readnone }
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