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e0f6c13cd6
Add the 16 access registers as LLVM registers. This allows removing a lot of special cases in the assembler and disassembler where we were handling access registers; this can all just use the generic register code now. Also add a bunch of instructions to operate on access registers, for assembler/disassembler use only. No change in code generation intended. llvm-svn: 286283
109 lines
3.4 KiB
C++
109 lines
3.4 KiB
C++
//===-- SystemZMCTargetDesc.h - SystemZ target descriptions -----*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_SYSTEMZ_MCTARGETDESC_SYSTEMZMCTARGETDESC_H
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#define LLVM_LIB_TARGET_SYSTEMZ_MCTARGETDESC_SYSTEMZMCTARGETDESC_H
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#include "llvm/Support/DataTypes.h"
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namespace llvm {
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class MCAsmBackend;
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class MCCodeEmitter;
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class MCContext;
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class MCInstrInfo;
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class MCObjectWriter;
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class MCRegisterInfo;
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class MCSubtargetInfo;
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class MCTargetOptions;
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class StringRef;
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class Target;
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class Triple;
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class raw_pwrite_stream;
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class raw_ostream;
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Target &getTheSystemZTarget();
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namespace SystemZMC {
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// How many bytes are in the ABI-defined, caller-allocated part of
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// a stack frame.
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const int64_t CallFrameSize = 160;
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// The offset of the DWARF CFA from the incoming stack pointer.
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const int64_t CFAOffsetFromInitialSP = CallFrameSize;
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// Maps of asm register numbers to LLVM register numbers, with 0 indicating
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// an invalid register. In principle we could use 32-bit and 64-bit register
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// classes directly, provided that we relegated the GPR allocation order
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// in SystemZRegisterInfo.td to an AltOrder and left the default order
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// as %r0-%r15. It seems better to provide the same interface for
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// all classes though.
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extern const unsigned GR32Regs[16];
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extern const unsigned GRH32Regs[16];
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extern const unsigned GR64Regs[16];
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extern const unsigned GR128Regs[16];
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extern const unsigned FP32Regs[16];
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extern const unsigned FP64Regs[16];
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extern const unsigned FP128Regs[16];
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extern const unsigned VR32Regs[32];
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extern const unsigned VR64Regs[32];
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extern const unsigned VR128Regs[32];
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extern const unsigned AR32Regs[16];
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// Return the 0-based number of the first architectural register that
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// contains the given LLVM register. E.g. R1D -> 1.
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unsigned getFirstReg(unsigned Reg);
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// Return the given register as a GR64.
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inline unsigned getRegAsGR64(unsigned Reg) {
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return GR64Regs[getFirstReg(Reg)];
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}
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// Return the given register as a low GR32.
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inline unsigned getRegAsGR32(unsigned Reg) {
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return GR32Regs[getFirstReg(Reg)];
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}
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// Return the given register as a high GR32.
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inline unsigned getRegAsGRH32(unsigned Reg) {
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return GRH32Regs[getFirstReg(Reg)];
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}
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// Return the given register as a VR128.
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inline unsigned getRegAsVR128(unsigned Reg) {
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return VR128Regs[getFirstReg(Reg)];
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}
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} // end namespace SystemZMC
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MCCodeEmitter *createSystemZMCCodeEmitter(const MCInstrInfo &MCII,
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const MCRegisterInfo &MRI,
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MCContext &Ctx);
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MCAsmBackend *createSystemZMCAsmBackend(const Target &T,
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const MCRegisterInfo &MRI,
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const Triple &TT, StringRef CPU,
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const MCTargetOptions &Options);
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MCObjectWriter *createSystemZObjectWriter(raw_pwrite_stream &OS, uint8_t OSABI);
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} // end namespace llvm
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// Defines symbolic names for SystemZ registers.
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// This defines a mapping from register name to register number.
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#define GET_REGINFO_ENUM
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#include "SystemZGenRegisterInfo.inc"
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// Defines symbolic names for the SystemZ instructions.
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#define GET_INSTRINFO_ENUM
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#include "SystemZGenInstrInfo.inc"
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#define GET_SUBTARGETINFO_ENUM
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#include "SystemZGenSubtargetInfo.inc"
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#endif
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