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8ea1e91e5d
There is no eBPF ISA support for BSWAP, ROTR, ROTL, SREM, SDIVREM, MULHU, ADDC, ADDE etc on i32. They could be emulated by other basic BPF_ALU operations, we'd set their lowering action the same as i64. Signed-off-by: Jiong Wang <jiong.wang@netronome.com> Reviewed-by: Yonghong Song <yhs@fb.com> llvm-svn: 325984
653 lines
22 KiB
C++
653 lines
22 KiB
C++
//===-- BPFISelLowering.cpp - BPF DAG Lowering Implementation ------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines the interfaces that BPF uses to lower LLVM code into a
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// selection DAG.
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//
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//===----------------------------------------------------------------------===//
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#include "BPFISelLowering.h"
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#include "BPF.h"
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#include "BPFSubtarget.h"
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#include "BPFTargetMachine.h"
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#include "llvm/CodeGen/CallingConvLower.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/SelectionDAGISel.h"
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#include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
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#include "llvm/CodeGen/ValueTypes.h"
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#include "llvm/IR/DiagnosticInfo.h"
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#include "llvm/IR/DiagnosticPrinter.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/Support/raw_ostream.h"
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using namespace llvm;
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#define DEBUG_TYPE "bpf-lower"
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static void fail(const SDLoc &DL, SelectionDAG &DAG, const Twine &Msg) {
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MachineFunction &MF = DAG.getMachineFunction();
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DAG.getContext()->diagnose(
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DiagnosticInfoUnsupported(MF.getFunction(), Msg, DL.getDebugLoc()));
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}
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static void fail(const SDLoc &DL, SelectionDAG &DAG, const char *Msg,
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SDValue Val) {
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MachineFunction &MF = DAG.getMachineFunction();
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std::string Str;
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raw_string_ostream OS(Str);
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OS << Msg;
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Val->print(OS);
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OS.flush();
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DAG.getContext()->diagnose(
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DiagnosticInfoUnsupported(MF.getFunction(), Str, DL.getDebugLoc()));
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}
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BPFTargetLowering::BPFTargetLowering(const TargetMachine &TM,
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const BPFSubtarget &STI)
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: TargetLowering(TM) {
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// Set up the register classes.
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addRegisterClass(MVT::i64, &BPF::GPRRegClass);
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// Compute derived properties from the register classes
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computeRegisterProperties(STI.getRegisterInfo());
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setStackPointerRegisterToSaveRestore(BPF::R11);
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setOperationAction(ISD::BR_CC, MVT::i64, Custom);
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setOperationAction(ISD::BR_JT, MVT::Other, Expand);
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setOperationAction(ISD::BRIND, MVT::Other, Expand);
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setOperationAction(ISD::BRCOND, MVT::Other, Expand);
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setOperationAction(ISD::SETCC, MVT::i64, Expand);
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setOperationAction(ISD::SELECT, MVT::i64, Expand);
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setOperationAction(ISD::SELECT_CC, MVT::i64, Custom);
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setOperationAction(ISD::GlobalAddress, MVT::i64, Custom);
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setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Custom);
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setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
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setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
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for (auto VT : { MVT::i32, MVT::i64 }) {
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if (VT == MVT::i32 && !STI.getHasAlu32())
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continue;
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setOperationAction(ISD::SDIVREM, VT, Expand);
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setOperationAction(ISD::UDIVREM, VT, Expand);
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setOperationAction(ISD::SREM, VT, Expand);
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setOperationAction(ISD::UREM, VT, Expand);
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setOperationAction(ISD::MULHU, VT, Expand);
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setOperationAction(ISD::MULHS, VT, Expand);
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setOperationAction(ISD::UMUL_LOHI, VT, Expand);
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setOperationAction(ISD::SMUL_LOHI, VT, Expand);
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setOperationAction(ISD::ADDC, VT, Expand);
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setOperationAction(ISD::ADDE, VT, Expand);
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setOperationAction(ISD::SUBC, VT, Expand);
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setOperationAction(ISD::SUBE, VT, Expand);
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setOperationAction(ISD::ROTR, VT, Expand);
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setOperationAction(ISD::ROTL, VT, Expand);
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setOperationAction(ISD::SHL_PARTS, VT, Expand);
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setOperationAction(ISD::SRL_PARTS, VT, Expand);
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setOperationAction(ISD::SRA_PARTS, VT, Expand);
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setOperationAction(ISD::CTPOP, VT, Expand);
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}
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if (STI.getHasAlu32())
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setOperationAction(ISD::BSWAP, MVT::i32, Expand);
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setOperationAction(ISD::CTTZ, MVT::i64, Custom);
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setOperationAction(ISD::CTLZ, MVT::i64, Custom);
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setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Custom);
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setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Custom);
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setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
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setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Expand);
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setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand);
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setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Expand);
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// Extended load operations for i1 types must be promoted
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for (MVT VT : MVT::integer_valuetypes()) {
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setLoadExtAction(ISD::EXTLOAD, VT, MVT::i1, Promote);
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setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i1, Promote);
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setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote);
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setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i8, Expand);
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setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i16, Expand);
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setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i32, Expand);
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}
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setBooleanContents(ZeroOrOneBooleanContent);
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// Function alignments (log2)
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setMinFunctionAlignment(3);
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setPrefFunctionAlignment(3);
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// inline memcpy() for kernel to see explicit copy
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MaxStoresPerMemset = MaxStoresPerMemsetOptSize = 128;
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MaxStoresPerMemcpy = MaxStoresPerMemcpyOptSize = 128;
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MaxStoresPerMemmove = MaxStoresPerMemmoveOptSize = 128;
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// CPU/Feature control
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HasAlu32 = STI.getHasAlu32();
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HasJmpExt = STI.getHasJmpExt();
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}
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bool BPFTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {
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return false;
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}
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std::pair<unsigned, const TargetRegisterClass *>
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BPFTargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
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StringRef Constraint,
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MVT VT) const {
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if (Constraint.size() == 1)
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// GCC Constraint Letters
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switch (Constraint[0]) {
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case 'r': // GENERAL_REGS
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return std::make_pair(0U, &BPF::GPRRegClass);
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default:
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break;
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}
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return TargetLowering::getRegForInlineAsmConstraint(TRI, Constraint, VT);
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}
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SDValue BPFTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
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switch (Op.getOpcode()) {
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case ISD::BR_CC:
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return LowerBR_CC(Op, DAG);
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case ISD::GlobalAddress:
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return LowerGlobalAddress(Op, DAG);
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case ISD::SELECT_CC:
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return LowerSELECT_CC(Op, DAG);
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default:
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llvm_unreachable("unimplemented operand");
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}
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}
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// Calling Convention Implementation
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#include "BPFGenCallingConv.inc"
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SDValue BPFTargetLowering::LowerFormalArguments(
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SDValue Chain, CallingConv::ID CallConv, bool IsVarArg,
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const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &DL,
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SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
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switch (CallConv) {
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default:
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report_fatal_error("Unsupported calling convention");
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case CallingConv::C:
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case CallingConv::Fast:
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break;
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}
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MachineFunction &MF = DAG.getMachineFunction();
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MachineRegisterInfo &RegInfo = MF.getRegInfo();
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// Assign locations to all of the incoming arguments.
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SmallVector<CCValAssign, 16> ArgLocs;
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CCState CCInfo(CallConv, IsVarArg, MF, ArgLocs, *DAG.getContext());
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CCInfo.AnalyzeFormalArguments(Ins, getHasAlu32() ? CC_BPF32 : CC_BPF64);
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for (auto &VA : ArgLocs) {
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if (VA.isRegLoc()) {
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// Arguments passed in registers
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EVT RegVT = VA.getLocVT();
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MVT::SimpleValueType SimpleTy = RegVT.getSimpleVT().SimpleTy;
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switch (SimpleTy) {
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default: {
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errs() << "LowerFormalArguments Unhandled argument type: "
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<< RegVT.getEVTString() << '\n';
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llvm_unreachable(0);
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}
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case MVT::i32:
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case MVT::i64:
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unsigned VReg = RegInfo.createVirtualRegister(SimpleTy == MVT::i64 ?
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&BPF::GPRRegClass :
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&BPF::GPR32RegClass);
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RegInfo.addLiveIn(VA.getLocReg(), VReg);
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SDValue ArgValue = DAG.getCopyFromReg(Chain, DL, VReg, RegVT);
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// If this is an value that has been promoted to wider types, insert an
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// assert[sz]ext to capture this, then truncate to the right size.
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if (VA.getLocInfo() == CCValAssign::SExt)
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ArgValue = DAG.getNode(ISD::AssertSext, DL, RegVT, ArgValue,
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DAG.getValueType(VA.getValVT()));
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else if (VA.getLocInfo() == CCValAssign::ZExt)
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ArgValue = DAG.getNode(ISD::AssertZext, DL, RegVT, ArgValue,
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DAG.getValueType(VA.getValVT()));
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if (VA.getLocInfo() != CCValAssign::Full)
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ArgValue = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), ArgValue);
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InVals.push_back(ArgValue);
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break;
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}
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} else {
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fail(DL, DAG, "defined with too many args");
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InVals.push_back(DAG.getConstant(0, DL, VA.getLocVT()));
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}
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}
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if (IsVarArg || MF.getFunction().hasStructRetAttr()) {
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fail(DL, DAG, "functions with VarArgs or StructRet are not supported");
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}
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return Chain;
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}
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const unsigned BPFTargetLowering::MaxArgs = 5;
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SDValue BPFTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
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SmallVectorImpl<SDValue> &InVals) const {
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SelectionDAG &DAG = CLI.DAG;
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auto &Outs = CLI.Outs;
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auto &OutVals = CLI.OutVals;
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auto &Ins = CLI.Ins;
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SDValue Chain = CLI.Chain;
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SDValue Callee = CLI.Callee;
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bool &IsTailCall = CLI.IsTailCall;
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CallingConv::ID CallConv = CLI.CallConv;
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bool IsVarArg = CLI.IsVarArg;
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MachineFunction &MF = DAG.getMachineFunction();
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// BPF target does not support tail call optimization.
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IsTailCall = false;
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switch (CallConv) {
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default:
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report_fatal_error("Unsupported calling convention");
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case CallingConv::Fast:
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case CallingConv::C:
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break;
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}
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// Analyze operands of the call, assigning locations to each operand.
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SmallVector<CCValAssign, 16> ArgLocs;
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CCState CCInfo(CallConv, IsVarArg, MF, ArgLocs, *DAG.getContext());
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CCInfo.AnalyzeCallOperands(Outs, getHasAlu32() ? CC_BPF32 : CC_BPF64);
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unsigned NumBytes = CCInfo.getNextStackOffset();
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if (Outs.size() > MaxArgs)
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fail(CLI.DL, DAG, "too many args to ", Callee);
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for (auto &Arg : Outs) {
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ISD::ArgFlagsTy Flags = Arg.Flags;
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if (!Flags.isByVal())
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continue;
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fail(CLI.DL, DAG, "pass by value not supported ", Callee);
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}
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auto PtrVT = getPointerTy(MF.getDataLayout());
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Chain = DAG.getCALLSEQ_START(Chain, NumBytes, 0, CLI.DL);
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SmallVector<std::pair<unsigned, SDValue>, MaxArgs> RegsToPass;
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// Walk arg assignments
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for (unsigned i = 0,
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e = std::min(static_cast<unsigned>(ArgLocs.size()), MaxArgs);
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i != e; ++i) {
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CCValAssign &VA = ArgLocs[i];
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SDValue Arg = OutVals[i];
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// Promote the value if needed.
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switch (VA.getLocInfo()) {
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default:
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llvm_unreachable("Unknown loc info");
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case CCValAssign::Full:
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break;
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case CCValAssign::SExt:
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Arg = DAG.getNode(ISD::SIGN_EXTEND, CLI.DL, VA.getLocVT(), Arg);
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break;
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case CCValAssign::ZExt:
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Arg = DAG.getNode(ISD::ZERO_EXTEND, CLI.DL, VA.getLocVT(), Arg);
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break;
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case CCValAssign::AExt:
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Arg = DAG.getNode(ISD::ANY_EXTEND, CLI.DL, VA.getLocVT(), Arg);
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break;
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}
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// Push arguments into RegsToPass vector
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if (VA.isRegLoc())
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RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
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else
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llvm_unreachable("call arg pass bug");
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}
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SDValue InFlag;
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// Build a sequence of copy-to-reg nodes chained together with token chain and
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// flag operands which copy the outgoing args into registers. The InFlag in
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// necessary since all emitted instructions must be stuck together.
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for (auto &Reg : RegsToPass) {
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Chain = DAG.getCopyToReg(Chain, CLI.DL, Reg.first, Reg.second, InFlag);
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InFlag = Chain.getValue(1);
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}
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// If the callee is a GlobalAddress node (quite common, every direct call is)
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// turn it into a TargetGlobalAddress node so that legalize doesn't hack it.
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// Likewise ExternalSymbol -> TargetExternalSymbol.
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if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
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Callee = DAG.getTargetGlobalAddress(G->getGlobal(), CLI.DL, PtrVT,
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G->getOffset(), 0);
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} else if (ExternalSymbolSDNode *E = dyn_cast<ExternalSymbolSDNode>(Callee)) {
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Callee = DAG.getTargetExternalSymbol(E->getSymbol(), PtrVT, 0);
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fail(CLI.DL, DAG, Twine("A call to built-in function '"
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+ StringRef(E->getSymbol())
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+ "' is not supported."));
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}
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// Returns a chain & a flag for retval copy to use.
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SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
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SmallVector<SDValue, 8> Ops;
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Ops.push_back(Chain);
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Ops.push_back(Callee);
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// Add argument registers to the end of the list so that they are
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// known live into the call.
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for (auto &Reg : RegsToPass)
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Ops.push_back(DAG.getRegister(Reg.first, Reg.second.getValueType()));
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if (InFlag.getNode())
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Ops.push_back(InFlag);
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Chain = DAG.getNode(BPFISD::CALL, CLI.DL, NodeTys, Ops);
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InFlag = Chain.getValue(1);
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// Create the CALLSEQ_END node.
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Chain = DAG.getCALLSEQ_END(
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Chain, DAG.getConstant(NumBytes, CLI.DL, PtrVT, true),
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DAG.getConstant(0, CLI.DL, PtrVT, true), InFlag, CLI.DL);
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InFlag = Chain.getValue(1);
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// Handle result values, copying them out of physregs into vregs that we
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// return.
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return LowerCallResult(Chain, InFlag, CallConv, IsVarArg, Ins, CLI.DL, DAG,
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InVals);
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}
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SDValue
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BPFTargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv,
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bool IsVarArg,
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const SmallVectorImpl<ISD::OutputArg> &Outs,
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const SmallVectorImpl<SDValue> &OutVals,
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const SDLoc &DL, SelectionDAG &DAG) const {
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unsigned Opc = BPFISD::RET_FLAG;
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// CCValAssign - represent the assignment of the return value to a location
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SmallVector<CCValAssign, 16> RVLocs;
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MachineFunction &MF = DAG.getMachineFunction();
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// CCState - Info about the registers and stack slot.
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CCState CCInfo(CallConv, IsVarArg, MF, RVLocs, *DAG.getContext());
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if (MF.getFunction().getReturnType()->isAggregateType()) {
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fail(DL, DAG, "only integer returns supported");
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return DAG.getNode(Opc, DL, MVT::Other, Chain);
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}
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// Analize return values.
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CCInfo.AnalyzeReturn(Outs, getHasAlu32() ? RetCC_BPF32 : RetCC_BPF64);
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SDValue Flag;
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SmallVector<SDValue, 4> RetOps(1, Chain);
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// Copy the result values into the output registers.
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for (unsigned i = 0; i != RVLocs.size(); ++i) {
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CCValAssign &VA = RVLocs[i];
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assert(VA.isRegLoc() && "Can only return in registers!");
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Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), OutVals[i], Flag);
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// Guarantee that all emitted copies are stuck together,
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// avoiding something bad.
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Flag = Chain.getValue(1);
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RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
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}
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RetOps[0] = Chain; // Update chain.
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// Add the flag if we have it.
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if (Flag.getNode())
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RetOps.push_back(Flag);
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return DAG.getNode(Opc, DL, MVT::Other, RetOps);
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}
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SDValue BPFTargetLowering::LowerCallResult(
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SDValue Chain, SDValue InFlag, CallingConv::ID CallConv, bool IsVarArg,
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const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &DL,
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SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
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MachineFunction &MF = DAG.getMachineFunction();
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// Assign locations to each value returned by this call.
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SmallVector<CCValAssign, 16> RVLocs;
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CCState CCInfo(CallConv, IsVarArg, MF, RVLocs, *DAG.getContext());
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if (Ins.size() >= 2) {
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fail(DL, DAG, "only small returns supported");
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for (unsigned i = 0, e = Ins.size(); i != e; ++i)
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InVals.push_back(DAG.getConstant(0, DL, Ins[i].VT));
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return DAG.getCopyFromReg(Chain, DL, 1, Ins[0].VT, InFlag).getValue(1);
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}
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CCInfo.AnalyzeCallResult(Ins, getHasAlu32() ? RetCC_BPF32 : RetCC_BPF64);
|
|
|
|
// Copy all of the result registers out of their specified physreg.
|
|
for (auto &Val : RVLocs) {
|
|
Chain = DAG.getCopyFromReg(Chain, DL, Val.getLocReg(),
|
|
Val.getValVT(), InFlag).getValue(1);
|
|
InFlag = Chain.getValue(2);
|
|
InVals.push_back(Chain.getValue(0));
|
|
}
|
|
|
|
return Chain;
|
|
}
|
|
|
|
static void NegateCC(SDValue &LHS, SDValue &RHS, ISD::CondCode &CC) {
|
|
switch (CC) {
|
|
default:
|
|
break;
|
|
case ISD::SETULT:
|
|
case ISD::SETULE:
|
|
case ISD::SETLT:
|
|
case ISD::SETLE:
|
|
CC = ISD::getSetCCSwappedOperands(CC);
|
|
std::swap(LHS, RHS);
|
|
break;
|
|
}
|
|
}
|
|
|
|
SDValue BPFTargetLowering::LowerBR_CC(SDValue Op, SelectionDAG &DAG) const {
|
|
SDValue Chain = Op.getOperand(0);
|
|
ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
|
|
SDValue LHS = Op.getOperand(2);
|
|
SDValue RHS = Op.getOperand(3);
|
|
SDValue Dest = Op.getOperand(4);
|
|
SDLoc DL(Op);
|
|
|
|
if (!getHasJmpExt())
|
|
NegateCC(LHS, RHS, CC);
|
|
|
|
return DAG.getNode(BPFISD::BR_CC, DL, Op.getValueType(), Chain, LHS, RHS,
|
|
DAG.getConstant(CC, DL, MVT::i64), Dest);
|
|
}
|
|
|
|
SDValue BPFTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const {
|
|
SDValue LHS = Op.getOperand(0);
|
|
SDValue RHS = Op.getOperand(1);
|
|
SDValue TrueV = Op.getOperand(2);
|
|
SDValue FalseV = Op.getOperand(3);
|
|
ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
|
|
SDLoc DL(Op);
|
|
|
|
if (!getHasJmpExt())
|
|
NegateCC(LHS, RHS, CC);
|
|
|
|
SDValue TargetCC = DAG.getConstant(CC, DL, MVT::i64);
|
|
|
|
SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
|
|
|
|
// The constant is expected at RHS in Select_Ri pattern.
|
|
if (isa<ConstantSDNode>(LHS.getNode()))
|
|
std::swap(LHS, RHS);
|
|
|
|
SDValue Ops[] = {LHS, RHS, TargetCC, TrueV, FalseV};
|
|
|
|
return DAG.getNode(BPFISD::SELECT_CC, DL, VTs, Ops);
|
|
}
|
|
|
|
const char *BPFTargetLowering::getTargetNodeName(unsigned Opcode) const {
|
|
switch ((BPFISD::NodeType)Opcode) {
|
|
case BPFISD::FIRST_NUMBER:
|
|
break;
|
|
case BPFISD::RET_FLAG:
|
|
return "BPFISD::RET_FLAG";
|
|
case BPFISD::CALL:
|
|
return "BPFISD::CALL";
|
|
case BPFISD::SELECT_CC:
|
|
return "BPFISD::SELECT_CC";
|
|
case BPFISD::BR_CC:
|
|
return "BPFISD::BR_CC";
|
|
case BPFISD::Wrapper:
|
|
return "BPFISD::Wrapper";
|
|
}
|
|
return nullptr;
|
|
}
|
|
|
|
SDValue BPFTargetLowering::LowerGlobalAddress(SDValue Op,
|
|
SelectionDAG &DAG) const {
|
|
auto N = cast<GlobalAddressSDNode>(Op);
|
|
assert(N->getOffset() == 0 && "Invalid offset for global address");
|
|
|
|
SDLoc DL(Op);
|
|
const GlobalValue *GV = N->getGlobal();
|
|
SDValue GA = DAG.getTargetGlobalAddress(GV, DL, MVT::i64);
|
|
|
|
return DAG.getNode(BPFISD::Wrapper, DL, MVT::i64, GA);
|
|
}
|
|
|
|
MachineBasicBlock *
|
|
BPFTargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI,
|
|
MachineBasicBlock *BB) const {
|
|
const TargetInstrInfo &TII = *BB->getParent()->getSubtarget().getInstrInfo();
|
|
DebugLoc DL = MI.getDebugLoc();
|
|
bool isSelectOp = MI.getOpcode() == BPF::Select;
|
|
|
|
assert((isSelectOp || MI.getOpcode() == BPF::Select_Ri) && "Unexpected instr type to insert");
|
|
|
|
// To "insert" a SELECT instruction, we actually have to insert the diamond
|
|
// control-flow pattern. The incoming instruction knows the destination vreg
|
|
// to set, the condition code register to branch on, the true/false values to
|
|
// select between, and a branch opcode to use.
|
|
const BasicBlock *LLVM_BB = BB->getBasicBlock();
|
|
MachineFunction::iterator I = ++BB->getIterator();
|
|
|
|
// ThisMBB:
|
|
// ...
|
|
// TrueVal = ...
|
|
// jmp_XX r1, r2 goto Copy1MBB
|
|
// fallthrough --> Copy0MBB
|
|
MachineBasicBlock *ThisMBB = BB;
|
|
MachineFunction *F = BB->getParent();
|
|
MachineBasicBlock *Copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
|
|
MachineBasicBlock *Copy1MBB = F->CreateMachineBasicBlock(LLVM_BB);
|
|
|
|
F->insert(I, Copy0MBB);
|
|
F->insert(I, Copy1MBB);
|
|
// Update machine-CFG edges by transferring all successors of the current
|
|
// block to the new block which will contain the Phi node for the select.
|
|
Copy1MBB->splice(Copy1MBB->begin(), BB,
|
|
std::next(MachineBasicBlock::iterator(MI)), BB->end());
|
|
Copy1MBB->transferSuccessorsAndUpdatePHIs(BB);
|
|
// Next, add the true and fallthrough blocks as its successors.
|
|
BB->addSuccessor(Copy0MBB);
|
|
BB->addSuccessor(Copy1MBB);
|
|
|
|
// Insert Branch if Flag
|
|
unsigned LHS = MI.getOperand(1).getReg();
|
|
int CC = MI.getOperand(3).getImm();
|
|
int NewCC;
|
|
switch (CC) {
|
|
case ISD::SETGT:
|
|
NewCC = isSelectOp ? BPF::JSGT_rr : BPF::JSGT_ri;
|
|
break;
|
|
case ISD::SETUGT:
|
|
NewCC = isSelectOp ? BPF::JUGT_rr : BPF::JUGT_ri;
|
|
break;
|
|
case ISD::SETGE:
|
|
NewCC = isSelectOp ? BPF::JSGE_rr : BPF::JSGE_ri;
|
|
break;
|
|
case ISD::SETUGE:
|
|
NewCC = isSelectOp ? BPF::JUGE_rr : BPF::JUGE_ri;
|
|
break;
|
|
case ISD::SETEQ:
|
|
NewCC = isSelectOp ? BPF::JEQ_rr : BPF::JEQ_ri;
|
|
break;
|
|
case ISD::SETNE:
|
|
NewCC = isSelectOp ? BPF::JNE_rr : BPF::JNE_ri;
|
|
break;
|
|
case ISD::SETLT:
|
|
NewCC = isSelectOp ? BPF::JSLT_rr : BPF::JSLT_ri;
|
|
break;
|
|
case ISD::SETULT:
|
|
NewCC = isSelectOp ? BPF::JULT_rr : BPF::JULT_ri;
|
|
break;
|
|
case ISD::SETLE:
|
|
NewCC = isSelectOp ? BPF::JSLE_rr : BPF::JSLE_ri;
|
|
break;
|
|
case ISD::SETULE:
|
|
NewCC = isSelectOp ? BPF::JULE_rr : BPF::JULE_ri;
|
|
break;
|
|
default:
|
|
report_fatal_error("unimplemented select CondCode " + Twine(CC));
|
|
}
|
|
if (isSelectOp)
|
|
BuildMI(BB, DL, TII.get(NewCC))
|
|
.addReg(LHS)
|
|
.addReg(MI.getOperand(2).getReg())
|
|
.addMBB(Copy1MBB);
|
|
else {
|
|
int64_t imm32 = MI.getOperand(2).getImm();
|
|
// sanity check before we build J*_ri instruction.
|
|
assert (isInt<32>(imm32));
|
|
BuildMI(BB, DL, TII.get(NewCC))
|
|
.addReg(LHS)
|
|
.addImm(imm32)
|
|
.addMBB(Copy1MBB);
|
|
}
|
|
|
|
// Copy0MBB:
|
|
// %FalseValue = ...
|
|
// # fallthrough to Copy1MBB
|
|
BB = Copy0MBB;
|
|
|
|
// Update machine-CFG edges
|
|
BB->addSuccessor(Copy1MBB);
|
|
|
|
// Copy1MBB:
|
|
// %Result = phi [ %FalseValue, Copy0MBB ], [ %TrueValue, ThisMBB ]
|
|
// ...
|
|
BB = Copy1MBB;
|
|
BuildMI(*BB, BB->begin(), DL, TII.get(BPF::PHI), MI.getOperand(0).getReg())
|
|
.addReg(MI.getOperand(5).getReg())
|
|
.addMBB(Copy0MBB)
|
|
.addReg(MI.getOperand(4).getReg())
|
|
.addMBB(ThisMBB);
|
|
|
|
MI.eraseFromParent(); // The pseudo instruction is gone now.
|
|
return BB;
|
|
}
|