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llvm-mirror/test/CodeGen/SystemZ/cmpxchg-05.ll
Jonas Paulsson d57759f053 [SystemZ] Reimplement the i8/i16 compare-and-swap logic.
Even though the implementation in emitAtomicCmpSwapW() was correct, it made
Valgrind report an error. Instead of using a RISBG on CmpVal, an LL[CH]R can
be made on the OldVal, and the problem is avoided.

Review: Ulrich Weigand

Differential Revision: https://reviews.llvm.org/D97604
2021-03-03 14:04:32 -06:00

56 lines
1.3 KiB
LLVM

; Test proper extension of 8-bit/16-bit cmpxchg.
;
; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
; CHECK-LABEL: f1
; CHECK: crjlh
; CHECK-NOT: llcr
; CHECK-NOT: cr
; CHECK: llgfr %r2, [[RES:%r[0-9]+]]
; CHECK-NOT: llcr
; CHECK-NOT: cr
define zeroext i8 @f1(i8* nocapture, i8 zeroext, i8 zeroext) {
%cx = cmpxchg i8* %0, i8 %1, i8 %2 seq_cst seq_cst
%res = extractvalue { i8, i1 } %cx, 0
ret i8 %res
}
; CHECK-LABEL: f2
; CHECK: crjlh
; CHECK-NOT: llhr
; CHECK-NOT: cr
; CHECK: llgfr %r2, [[RES:%r[0-9]+]]
; CHECK-NOT: llhr
; CHECK-NOT: cr
define zeroext i16 @f2(i16* nocapture, i16 zeroext, i16 zeroext) {
%cx = cmpxchg i16* %0, i16 %1, i16 %2 seq_cst seq_cst
%res = extractvalue { i16, i1 } %cx, 0
ret i16 %res
}
; CHECK-LABEL: f3
; CHECK: crjlh
; CHECK-NOT: llcr
; CHECK-NOT: cr
; CHECK: lgbr %r2, [[RES:%r[0-9]+]]
; CHECK-NOT: llcr
; CHECK-NOT: cr
define signext i8 @f3(i8* nocapture, i8 signext, i8 signext) {
%cx = cmpxchg i8* %0, i8 %1, i8 %2 seq_cst seq_cst
%res = extractvalue { i8, i1 } %cx, 0
ret i8 %res
}
; CHECK-LABEL: f4
; CHECK: crjlh
; CHECK-NOT: llhr
; CHECK-NOT: cr
; CHECK: lghr %r2, [[RES:%r[0-9]+]]
; CHECK-NOT: llhr
; CHECK-NOT: cr
define signext i16 @f4(i16* nocapture, i16 signext, i16 signext) {
%cx = cmpxchg i16* %0, i16 %1, i16 %2 seq_cst seq_cst
%res = extractvalue { i16, i1 } %cx, 0
ret i16 %res
}