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0f000465c2
This patch aims to reduce spilling and register moves by using the 3-address versions of instructions per default instead of the 2-address equivalent ones. It seems that both spilling and register moves are improved noticeably generally. Regalloc hints are passed to increase conversions to 2-address instructions which are done in SystemZShortenInst.cpp (after regalloc). Since the SystemZ reg/mem instructions are 2-address (dst and lhs regs are the same), foldMemoryOperandImpl() can no longer trivially fold a spilled source register since the reg/reg instruction is now 3-address. In order to remedy this, new 3-address pseudo memory instructions are used to perform the folding only when the dst and lhs virtual registers are known to be allocated to the same physreg. In order to not let MachineCopyPropagation run and change registers on these transformed instructions (making it 3-address), a new target pass called SystemZPostRewrite.cpp is run just after VirtRegRewriter, that immediately lowers the pseudo to a target instruction. If it would have been possibe to insert a COPY instruction and change a register operand (convert to 2-address) in foldMemoryOperandImpl() while trusting that the caller (e.g. InlineSpiller) would update/repair the involved LiveIntervals, the solution involving pseudo instructions would not have been needed. This is perhaps a potential improvement (see Phabricator post). Common code changes: * A new hook TargetPassConfig::addPostRewrite() is utilized to be able to run a target pass immediately before MachineCopyPropagation. * VirtRegMap is passed as an argument to foldMemoryOperand(). Review: Ulrich Weigand, Quentin Colombet https://reviews.llvm.org/D60888 llvm-svn: 362868
143 lines
3.7 KiB
LLVM
143 lines
3.7 KiB
LLVM
; Test 64-bit addition in which the second operand is variable.
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;
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; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z10 | FileCheck %s --check-prefixes=CHECK,Z10
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; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z196 | FileCheck %s --check-prefixes=CHECK,Z196
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declare i64 @foo()
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; Check AGR.
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define i64 @f1(i64 %a, i64 %b) {
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; CHECK-LABEL: f1:
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; CHECK: agr %r2, %r3
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; CHECK: br %r14
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%add = add i64 %a, %b
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ret i64 %add
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}
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; Check AG with no displacement.
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define i64 @f2(i64 %a, i64 *%src) {
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; CHECK-LABEL: f2:
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; CHECK: ag %r2, 0(%r3)
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; CHECK: br %r14
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%b = load i64, i64 *%src
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%add = add i64 %a, %b
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ret i64 %add
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}
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; Check the high end of the aligned AG range.
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define i64 @f3(i64 %a, i64 *%src) {
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; CHECK-LABEL: f3:
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; CHECK: ag %r2, 524280(%r3)
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; CHECK: br %r14
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%ptr = getelementptr i64, i64 *%src, i64 65535
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%b = load i64, i64 *%ptr
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%add = add i64 %a, %b
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ret i64 %add
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}
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; Check the next doubleword up, which needs separate address logic.
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; Other sequences besides this one would be OK.
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define i64 @f4(i64 %a, i64 *%src) {
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; CHECK-LABEL: f4:
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; CHECK: agfi %r3, 524288
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; CHECK: ag %r2, 0(%r3)
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; CHECK: br %r14
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%ptr = getelementptr i64, i64 *%src, i64 65536
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%b = load i64, i64 *%ptr
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%add = add i64 %a, %b
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ret i64 %add
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}
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; Check the high end of the negative aligned AG range.
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define i64 @f5(i64 %a, i64 *%src) {
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; CHECK-LABEL: f5:
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; CHECK: ag %r2, -8(%r3)
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; CHECK: br %r14
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%ptr = getelementptr i64, i64 *%src, i64 -1
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%b = load i64, i64 *%ptr
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%add = add i64 %a, %b
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ret i64 %add
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}
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; Check the low end of the AG range.
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define i64 @f6(i64 %a, i64 *%src) {
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; CHECK-LABEL: f6:
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; CHECK: ag %r2, -524288(%r3)
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; CHECK: br %r14
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%ptr = getelementptr i64, i64 *%src, i64 -65536
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%b = load i64, i64 *%ptr
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%add = add i64 %a, %b
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ret i64 %add
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}
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; Check the next doubleword down, which needs separate address logic.
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; Other sequences besides this one would be OK.
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define i64 @f7(i64 %a, i64 *%src) {
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; CHECK-LABEL: f7:
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; CHECK: agfi %r3, -524296
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; CHECK: ag %r2, 0(%r3)
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; CHECK: br %r14
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%ptr = getelementptr i64, i64 *%src, i64 -65537
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%b = load i64, i64 *%ptr
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%add = add i64 %a, %b
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ret i64 %add
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}
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; Check that AG allows an index.
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define i64 @f8(i64 %a, i64 %src, i64 %index) {
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; CHECK-LABEL: f8:
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; CHECK: ag %r2, 524280({{%r4,%r3|%r3,%r4}})
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; CHECK: br %r14
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%add1 = add i64 %src, %index
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%add2 = add i64 %add1, 524280
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%ptr = inttoptr i64 %add2 to i64 *
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%b = load i64, i64 *%ptr
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%add = add i64 %a, %b
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ret i64 %add
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}
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; Check that additions of spilled values can use AG rather than AGR.
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; Note: Z196 is suboptimal with one unfolded reload.
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define i64 @f9(i64 *%ptr0) {
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; CHECK-LABEL: f9:
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; CHECK: brasl %r14, foo@PLT
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; Z10: ag %r2, 168(%r15)
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; Z196: ag %r0, 168(%r15)
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; CHECK: br %r14
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%ptr1 = getelementptr i64, i64 *%ptr0, i64 2
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%ptr2 = getelementptr i64, i64 *%ptr0, i64 4
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%ptr3 = getelementptr i64, i64 *%ptr0, i64 6
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%ptr4 = getelementptr i64, i64 *%ptr0, i64 8
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%ptr5 = getelementptr i64, i64 *%ptr0, i64 10
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%ptr6 = getelementptr i64, i64 *%ptr0, i64 12
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%ptr7 = getelementptr i64, i64 *%ptr0, i64 14
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%ptr8 = getelementptr i64, i64 *%ptr0, i64 16
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%ptr9 = getelementptr i64, i64 *%ptr0, i64 18
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%val0 = load i64, i64 *%ptr0
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%val1 = load i64, i64 *%ptr1
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%val2 = load i64, i64 *%ptr2
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%val3 = load i64, i64 *%ptr3
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%val4 = load i64, i64 *%ptr4
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%val5 = load i64, i64 *%ptr5
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%val6 = load i64, i64 *%ptr6
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%val7 = load i64, i64 *%ptr7
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%val8 = load i64, i64 *%ptr8
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%val9 = load i64, i64 *%ptr9
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%ret = call i64 @foo()
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%add0 = add i64 %ret, %val0
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%add1 = add i64 %add0, %val1
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%add2 = add i64 %add1, %val2
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%add3 = add i64 %add2, %val3
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%add4 = add i64 %add3, %val4
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%add5 = add i64 %add4, %val5
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%add6 = add i64 %add5, %val6
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%add7 = add i64 %add6, %val7
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%add8 = add i64 %add7, %val8
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%add9 = add i64 %add8, %val9
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ret i64 %add9
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}
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