1
0
mirror of https://github.com/RPCS3/llvm-mirror.git synced 2024-11-23 11:13:28 +01:00
llvm-mirror/unittests/CodeGen
Jessica Paquette ed1a930649 [GlobalISel] Implement computeKnownBits for G_SEXT_INREG
Just use the existing `Known.sextInReg` implementation.

- Update KnownBitsTest.cpp.
- Update combine-redundant-and.mir for a more concrete example.

Differential Revision: https://reviews.llvm.org/D95484
2021-01-26 15:01:38 -08:00
..
GlobalISel [GlobalISel] Implement computeKnownBits for G_SEXT_INREG 2021-01-26 15:01:38 -08:00
AArch64SelectionDAGTest.cpp
AllocationOrderTest.cpp
AsmPrinterDwarfTest.cpp make the AsmPrinterHandler array public 2020-11-03 10:02:09 -05:00
CMakeLists.txt [SelectionDAG] Avoid aliasing analysis if the object size is unknown. 2020-11-25 06:13:37 +08:00
DIEHashTest.cpp
DIETest.cpp
LexicalScopesTest.cpp [docs][unittest][Go][StackProtector] Migrate deprecated DebugInfo::get to DILocation::get 2020-12-15 14:17:04 -08:00
LowLevelTypeTest.cpp
MachineInstrBundleIteratorTest.cpp
MachineInstrTest.cpp Switch from llvm::is_trivially_copyable to std::is_trivially_copyable 2020-12-02 22:02:48 -08:00
MachineOperandTest.cpp
MFCommon.inc
PassManagerTest.cpp
ScalableVectorMVTsTest.cpp
SelectionDAGAddressAnalysisTest.cpp [SelectionDAG] Avoid aliasing analysis if the object size is unknown. 2020-11-25 06:13:37 +08:00
TargetOptionsTest.cpp
TestAsmPrinter.cpp
TestAsmPrinter.h make the AsmPrinterHandler array public 2020-11-03 10:02:09 -05:00
TypeTraitsTest.cpp Switch from llvm::is_trivially_copyable to std::is_trivially_copyable 2020-12-02 22:02:48 -08:00