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487ffb554f
The main caller of this already has an MVT and several targets called getSimpleVT inside without checking isSimple. This makes the simpleness explicit. llvm-svn: 346180
463 lines
21 KiB
C++
463 lines
21 KiB
C++
//===-- HexagonISelLowering.h - Hexagon DAG Lowering Interface --*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines the interfaces that Hexagon uses to lower LLVM code into a
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// selection DAG.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_HEXAGON_HEXAGONISELLOWERING_H
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#define LLVM_LIB_TARGET_HEXAGON_HEXAGONISELLOWERING_H
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#include "Hexagon.h"
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#include "llvm/ADT/StringRef.h"
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#include "llvm/CodeGen/ISDOpcodes.h"
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#include "llvm/CodeGen/SelectionDAGNodes.h"
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#include "llvm/CodeGen/TargetLowering.h"
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#include "llvm/CodeGen/ValueTypes.h"
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#include "llvm/IR/CallingConv.h"
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#include "llvm/IR/InlineAsm.h"
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#include "llvm/Support/MachineValueType.h"
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#include <cstdint>
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#include <utility>
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namespace llvm {
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namespace HexagonISD {
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enum NodeType : unsigned {
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OP_BEGIN = ISD::BUILTIN_OP_END,
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CONST32 = OP_BEGIN,
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CONST32_GP, // For marking data present in GP.
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ADDC, // Add with carry: (X, Y, Cin) -> (X+Y, Cout).
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SUBC, // Sub with carry: (X, Y, Cin) -> (X+~Y+Cin, Cout).
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ALLOCA,
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AT_GOT, // Index in GOT.
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AT_PCREL, // Offset relative to PC.
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CALL, // Function call.
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CALLnr, // Function call that does not return.
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CALLR,
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RET_FLAG, // Return with a flag operand.
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BARRIER, // Memory barrier.
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JT, // Jump table.
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CP, // Constant pool.
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COMBINE,
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VSPLAT, // Generic splat, selection depends on argument/return
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// types.
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VASL,
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VASR,
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VLSR,
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TSTBIT,
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INSERT,
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EXTRACTU,
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VEXTRACTW,
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VINSERTW0,
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VROR,
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TC_RETURN,
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EH_RETURN,
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DCFETCH,
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READCYCLE,
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D2P, // Convert 8-byte value to 8-bit predicate register. [*]
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P2D, // Convert 8-bit predicate register to 8-byte value. [*]
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V2Q, // Convert HVX vector to a vector predicate reg. [*]
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Q2V, // Convert vector predicate to an HVX vector. [*]
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// [*] The equivalence is defined as "Q <=> (V != 0)",
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// where the != operation compares bytes.
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// Note: V != 0 is implemented as V >u 0.
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QCAT,
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QTRUE,
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QFALSE,
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VZERO,
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VSPLATW, // HVX splat of a 32-bit word with an arbitrary result type.
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TYPECAST, // No-op that's used to convert between different legal
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// types in a register.
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VALIGN, // Align two vectors (in Op0, Op1) to one that would have
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// been loaded from address in Op2.
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VALIGNADDR, // Align vector address: Op0 & -Op1, except when it is
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// an address in a vector load, then it's a no-op.
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OP_END
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};
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} // end namespace HexagonISD
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class HexagonSubtarget;
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class HexagonTargetLowering : public TargetLowering {
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int VarArgsFrameOffset; // Frame offset to start of varargs area.
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const HexagonTargetMachine &HTM;
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const HexagonSubtarget &Subtarget;
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bool CanReturnSmallStruct(const Function* CalleeFn, unsigned& RetSize)
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const;
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public:
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explicit HexagonTargetLowering(const TargetMachine &TM,
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const HexagonSubtarget &ST);
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bool isHVXVectorType(MVT Ty) const;
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/// IsEligibleForTailCallOptimization - Check whether the call is eligible
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/// for tail call optimization. Targets which want to do tail call
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/// optimization should implement this function.
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bool IsEligibleForTailCallOptimization(SDValue Callee,
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CallingConv::ID CalleeCC, bool isVarArg, bool isCalleeStructRet,
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bool isCallerStructRet, const SmallVectorImpl<ISD::OutputArg> &Outs,
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const SmallVectorImpl<SDValue> &OutVals,
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const SmallVectorImpl<ISD::InputArg> &Ins, SelectionDAG& DAG) const;
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bool getTgtMemIntrinsic(IntrinsicInfo &Info, const CallInst &I,
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MachineFunction &MF,
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unsigned Intrinsic) const override;
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bool isTruncateFree(Type *Ty1, Type *Ty2) const override;
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bool isTruncateFree(EVT VT1, EVT VT2) const override;
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bool isCheapToSpeculateCttz() const override { return true; }
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bool isCheapToSpeculateCtlz() const override { return true; }
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bool isCtlzFast() const override { return true; }
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bool allowTruncateForTailCall(Type *Ty1, Type *Ty2) const override;
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/// Return true if an FMA operation is faster than a pair of mul and add
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/// instructions. fmuladd intrinsics will be expanded to FMAs when this
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/// method returns true (and FMAs are legal), otherwise fmuladd is
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/// expanded to mul + add.
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bool isFMAFasterThanFMulAndFAdd(EVT) const override;
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// Should we expand the build vector with shuffles?
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bool shouldExpandBuildVectorWithShuffles(EVT VT,
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unsigned DefinedValues) const override;
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bool isShuffleMaskLegal(ArrayRef<int> Mask, EVT VT) const override;
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TargetLoweringBase::LegalizeTypeAction getPreferredVectorAction(MVT VT)
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const override;
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SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
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void LowerOperationWrapper(SDNode *N, SmallVectorImpl<SDValue> &Results,
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SelectionDAG &DAG) const override;
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void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue> &Results,
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SelectionDAG &DAG) const override;
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const char *getTargetNodeName(unsigned Opcode) const override;
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SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerEXTRACT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerINSERT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerVECTOR_SHIFT(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerROTL(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerBITCAST(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerANY_EXTEND(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerSIGN_EXTEND(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerZERO_EXTEND(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerLoad(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerStore(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerUnalignedLoad(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerAddSubCarry(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerINLINEASM(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerPREFETCH(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerREADCYCLECOUNTER(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerEH_LABEL(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const;
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SDValue
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LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
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const SmallVectorImpl<ISD::InputArg> &Ins,
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const SDLoc &dl, SelectionDAG &DAG,
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SmallVectorImpl<SDValue> &InVals) const override;
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SDValue LowerGLOBALADDRESS(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerToTLSGeneralDynamicModel(GlobalAddressSDNode *GA,
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SelectionDAG &DAG) const;
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SDValue LowerToTLSInitialExecModel(GlobalAddressSDNode *GA,
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SelectionDAG &DAG) const;
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SDValue LowerToTLSLocalExecModel(GlobalAddressSDNode *GA,
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SelectionDAG &DAG) const;
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SDValue GetDynamicTLSAddr(SelectionDAG &DAG, SDValue Chain,
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GlobalAddressSDNode *GA, SDValue InFlag, EVT PtrVT,
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unsigned ReturnReg, unsigned char OperandFlags) const;
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SDValue LowerGLOBAL_OFFSET_TABLE(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerCall(TargetLowering::CallLoweringInfo &CLI,
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SmallVectorImpl<SDValue> &InVals) const override;
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SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
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CallingConv::ID CallConv, bool isVarArg,
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const SmallVectorImpl<ISD::InputArg> &Ins,
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const SDLoc &dl, SelectionDAG &DAG,
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SmallVectorImpl<SDValue> &InVals,
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const SmallVectorImpl<SDValue> &OutVals,
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SDValue Callee) const;
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SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerVSELECT(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerATOMIC_FENCE(SDValue Op, SelectionDAG& DAG) const;
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SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
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bool CanLowerReturn(CallingConv::ID CallConv,
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MachineFunction &MF, bool isVarArg,
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const SmallVectorImpl<ISD::OutputArg> &Outs,
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LLVMContext &Context) const override;
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SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
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const SmallVectorImpl<ISD::OutputArg> &Outs,
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const SmallVectorImpl<SDValue> &OutVals,
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const SDLoc &dl, SelectionDAG &DAG) const override;
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bool mayBeEmittedAsTailCall(const CallInst *CI) const override;
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unsigned getRegisterByName(const char* RegName, EVT VT,
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SelectionDAG &DAG) const override;
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/// If a physical register, this returns the register that receives the
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/// exception address on entry to an EH pad.
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unsigned
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getExceptionPointerRegister(const Constant *PersonalityFn) const override {
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return Hexagon::R0;
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}
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/// If a physical register, this returns the register that receives the
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/// exception typeid on entry to a landing pad.
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unsigned
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getExceptionSelectorRegister(const Constant *PersonalityFn) const override {
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return Hexagon::R1;
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}
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SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG) const;
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EVT getSetCCResultType(const DataLayout &, LLVMContext &C,
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EVT VT) const override {
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if (!VT.isVector())
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return MVT::i1;
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else
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return EVT::getVectorVT(C, MVT::i1, VT.getVectorNumElements());
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}
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bool getPostIndexedAddressParts(SDNode *N, SDNode *Op,
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SDValue &Base, SDValue &Offset,
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ISD::MemIndexedMode &AM,
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SelectionDAG &DAG) const override;
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ConstraintType getConstraintType(StringRef Constraint) const override;
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std::pair<unsigned, const TargetRegisterClass *>
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getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
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StringRef Constraint, MVT VT) const override;
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unsigned
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getInlineAsmMemConstraint(StringRef ConstraintCode) const override {
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if (ConstraintCode == "o")
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return InlineAsm::Constraint_o;
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return TargetLowering::getInlineAsmMemConstraint(ConstraintCode);
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}
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// Intrinsics
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SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerINTRINSIC_VOID(SDValue Op, SelectionDAG &DAG) const;
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/// isLegalAddressingMode - Return true if the addressing mode represented
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/// by AM is legal for this target, for a load/store of the specified type.
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/// The type may be VoidTy, in which case only return true if the addressing
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/// mode is legal for a load/store of any legal type.
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/// TODO: Handle pre/postinc as well.
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bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM,
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Type *Ty, unsigned AS,
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Instruction *I = nullptr) const override;
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/// Return true if folding a constant offset with the given GlobalAddress
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/// is legal. It is frequently not legal in PIC relocation models.
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bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override;
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bool isFPImmLegal(const APFloat &Imm, EVT VT) const override;
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/// isLegalICmpImmediate - Return true if the specified immediate is legal
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/// icmp immediate, that is the target has icmp instructions which can
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/// compare a register against the immediate without having to materialize
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/// the immediate into a register.
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bool isLegalICmpImmediate(int64_t Imm) const override;
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EVT getOptimalMemOpType(uint64_t Size, unsigned DstAlign,
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unsigned SrcAlign, bool IsMemset, bool ZeroMemset, bool MemcpyStrSrc,
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MachineFunction &MF) const override;
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bool allowsMisalignedMemoryAccesses(EVT VT, unsigned AddrSpace,
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unsigned Align, bool *Fast) const override;
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/// Returns relocation base for the given PIC jumptable.
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SDValue getPICJumpTableRelocBase(SDValue Table, SelectionDAG &DAG)
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const override;
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bool shouldReduceLoadWidth(SDNode *Load, ISD::LoadExtType ExtTy,
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EVT NewVT) const override;
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// Handling of atomic RMW instructions.
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Value *emitLoadLinked(IRBuilder<> &Builder, Value *Addr,
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AtomicOrdering Ord) const override;
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Value *emitStoreConditional(IRBuilder<> &Builder, Value *Val,
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Value *Addr, AtomicOrdering Ord) const override;
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AtomicExpansionKind shouldExpandAtomicLoadInIR(LoadInst *LI) const override;
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bool shouldExpandAtomicStoreInIR(StoreInst *SI) const override;
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AtomicExpansionKind
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shouldExpandAtomicCmpXchgInIR(AtomicCmpXchgInst *AI) const override;
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AtomicExpansionKind
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shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const override {
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return AtomicExpansionKind::LLSC;
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}
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private:
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void initializeHVXLowering();
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void validateConstPtrAlignment(SDValue Ptr, const SDLoc &dl,
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unsigned NeedAlign) const;
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std::pair<SDValue,int> getBaseAndOffset(SDValue Addr) const;
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bool getBuildVectorConstInts(ArrayRef<SDValue> Values, MVT VecTy,
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SelectionDAG &DAG,
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MutableArrayRef<ConstantInt*> Consts) const;
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SDValue buildVector32(ArrayRef<SDValue> Elem, const SDLoc &dl, MVT VecTy,
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SelectionDAG &DAG) const;
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SDValue buildVector64(ArrayRef<SDValue> Elem, const SDLoc &dl, MVT VecTy,
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SelectionDAG &DAG) const;
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SDValue extractVector(SDValue VecV, SDValue IdxV, const SDLoc &dl,
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MVT ValTy, MVT ResTy, SelectionDAG &DAG) const;
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SDValue insertVector(SDValue VecV, SDValue ValV, SDValue IdxV,
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const SDLoc &dl, MVT ValTy, SelectionDAG &DAG) const;
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SDValue expandPredicate(SDValue Vec32, const SDLoc &dl,
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SelectionDAG &DAG) const;
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SDValue contractPredicate(SDValue Vec64, const SDLoc &dl,
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SelectionDAG &DAG) const;
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SDValue getVectorShiftByInt(SDValue Op, SelectionDAG &DAG) const;
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bool isUndef(SDValue Op) const {
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if (Op.isMachineOpcode())
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return Op.getMachineOpcode() == TargetOpcode::IMPLICIT_DEF;
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return Op.getOpcode() == ISD::UNDEF;
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}
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SDValue getInstr(unsigned MachineOpc, const SDLoc &dl, MVT Ty,
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ArrayRef<SDValue> Ops, SelectionDAG &DAG) const {
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SDNode *N = DAG.getMachineNode(MachineOpc, dl, Ty, Ops);
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return SDValue(N, 0);
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}
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SDValue getZero(const SDLoc &dl, MVT Ty, SelectionDAG &DAG) const;
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using VectorPair = std::pair<SDValue, SDValue>;
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using TypePair = std::pair<MVT, MVT>;
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SDValue getInt(unsigned IntId, MVT ResTy, ArrayRef<SDValue> Ops,
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const SDLoc &dl, SelectionDAG &DAG) const;
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MVT ty(SDValue Op) const {
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return Op.getValueType().getSimpleVT();
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}
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TypePair ty(const VectorPair &Ops) const {
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return { Ops.first.getValueType().getSimpleVT(),
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Ops.second.getValueType().getSimpleVT() };
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}
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MVT tyScalar(MVT Ty) const {
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if (!Ty.isVector())
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return Ty;
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return MVT::getIntegerVT(Ty.getSizeInBits());
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}
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MVT tyVector(MVT Ty, MVT ElemTy) const {
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if (Ty.isVector() && Ty.getVectorElementType() == ElemTy)
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return Ty;
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unsigned TyWidth = Ty.getSizeInBits();
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unsigned ElemWidth = ElemTy.getSizeInBits();
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assert((TyWidth % ElemWidth) == 0);
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return MVT::getVectorVT(ElemTy, TyWidth/ElemWidth);
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}
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MVT typeJoin(const TypePair &Tys) const;
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TypePair typeSplit(MVT Ty) const;
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MVT typeExtElem(MVT VecTy, unsigned Factor) const;
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MVT typeTruncElem(MVT VecTy, unsigned Factor) const;
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SDValue opJoin(const VectorPair &Ops, const SDLoc &dl,
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SelectionDAG &DAG) const;
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VectorPair opSplit(SDValue Vec, const SDLoc &dl, SelectionDAG &DAG) const;
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SDValue opCastElem(SDValue Vec, MVT ElemTy, SelectionDAG &DAG) const;
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bool isHvxSingleTy(MVT Ty) const;
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bool isHvxPairTy(MVT Ty) const;
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SDValue convertToByteIndex(SDValue ElemIdx, MVT ElemTy,
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SelectionDAG &DAG) const;
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SDValue getIndexInWord32(SDValue Idx, MVT ElemTy, SelectionDAG &DAG) const;
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SDValue getByteShuffle(const SDLoc &dl, SDValue Op0, SDValue Op1,
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ArrayRef<int> Mask, SelectionDAG &DAG) const;
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SDValue buildHvxVectorReg(ArrayRef<SDValue> Values, const SDLoc &dl,
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MVT VecTy, SelectionDAG &DAG) const;
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SDValue buildHvxVectorPred(ArrayRef<SDValue> Values, const SDLoc &dl,
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MVT VecTy, SelectionDAG &DAG) const;
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SDValue createHvxPrefixPred(SDValue PredV, const SDLoc &dl,
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unsigned BitBytes, bool ZeroFill,
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SelectionDAG &DAG) const;
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SDValue extractHvxElementReg(SDValue VecV, SDValue IdxV, const SDLoc &dl,
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MVT ResTy, SelectionDAG &DAG) const;
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SDValue extractHvxElementPred(SDValue VecV, SDValue IdxV, const SDLoc &dl,
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MVT ResTy, SelectionDAG &DAG) const;
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SDValue insertHvxElementReg(SDValue VecV, SDValue IdxV, SDValue ValV,
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const SDLoc &dl, SelectionDAG &DAG) const;
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SDValue insertHvxElementPred(SDValue VecV, SDValue IdxV, SDValue ValV,
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const SDLoc &dl, SelectionDAG &DAG) const;
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SDValue extractHvxSubvectorReg(SDValue VecV, SDValue IdxV, const SDLoc &dl,
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MVT ResTy, SelectionDAG &DAG) const;
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SDValue extractHvxSubvectorPred(SDValue VecV, SDValue IdxV, const SDLoc &dl,
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MVT ResTy, SelectionDAG &DAG) const;
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SDValue insertHvxSubvectorReg(SDValue VecV, SDValue SubV, SDValue IdxV,
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const SDLoc &dl, SelectionDAG &DAG) const;
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SDValue insertHvxSubvectorPred(SDValue VecV, SDValue SubV, SDValue IdxV,
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const SDLoc &dl, SelectionDAG &DAG) const;
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SDValue extendHvxVectorPred(SDValue VecV, const SDLoc &dl, MVT ResTy,
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bool ZeroExt, SelectionDAG &DAG) const;
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SDValue LowerHvxBuildVector(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerHvxConcatVectors(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerHvxExtractElement(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerHvxInsertElement(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerHvxExtractSubvector(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerHvxInsertSubvector(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerHvxAnyExt(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerHvxSignExt(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerHvxZeroExt(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerHvxCttz(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerHvxMul(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerHvxMulh(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerHvxSetCC(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerHvxExtend(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerHvxShift(SDValue Op, SelectionDAG &DAG) const;
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SDValue SplitHvxPairOp(SDValue Op, SelectionDAG &DAG) const;
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SDValue SplitHvxMemOp(SDValue Op, SelectionDAG &DAG) const;
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std::pair<const TargetRegisterClass*, uint8_t>
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findRepresentativeClass(const TargetRegisterInfo *TRI, MVT VT)
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const override;
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bool isHvxOperation(SDValue Op) const;
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SDValue LowerHvxOperation(SDValue Op, SelectionDAG &DAG) const;
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};
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} // end namespace llvm
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#endif // LLVM_LIB_TARGET_HEXAGON_HEXAGONISELLOWERING_H
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