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60ee3e2e8b
The DAG behavior allows matchching input patterns with a single result to the first result of an output instruction that defines multiple results. The remaining defs are implicitly dead. This starts to fix using manual selection for AMDGPU add/sub (although it's still needed, mostly because it's also still needed for G_PTR_ADD).
28 lines
1.5 KiB
TableGen
28 lines
1.5 KiB
TableGen
// RUN: llvm-tblgen -gen-global-isel -warn-on-skipped-patterns -I %p/../../include -I %p/Common %s -o - < %s | FileCheck -check-prefix=GISEL %s
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include "llvm/Target/Target.td"
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include "GlobalISelEmitterCommon.td"
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// Test that extra explicit results are treated as dead defs.
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def ADD_CO : I<(outs GPR32:$dst, GPR8:$flag),
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(ins GPR32Op:$src0, GPR32Op:$src1), []>;
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// GISEL: GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_ADD,
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// GISEL-NEXT: GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
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// GISEL-NEXT: GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
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// GISEL-NEXT: GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
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// GISEL-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/MyTarget::GPR32RegClassID,
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// GISEL-NEXT: // (add:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1) => (ADD_CO:{ *:[i32] }:{ *:[i8] } GPR32:{ *:[i32] }:$src0, GPR32:{ *:[i32] }:$src1)
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// GISEL-NEXT: GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s8,
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// GISEL-NEXT: GIR_BuildMI, /*InsnID*/0, /*Opcode*/MyTarget::ADD_CO,
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// GISEL-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
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// GISEL-NEXT: GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/RegState::Define|RegState::Dead,
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// GISEL-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
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// GISEL-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
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// GISEL-NEXT: GIR_EraseFromParent, /*InsnID*/0,
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// GISEL-NEXT: GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
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def : Pat <
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(add i32:$src0, i32:$src1),
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(ADD_CO GPR32:$src0, GPR32:$src1)
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>;
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