Sanne Wouda 3f70a4c2df [AArch64] Fix over-eager fusing of NEON SIMD MUL/ADD ... Summary: The ISel pattern for SIMD MLA is a bit too eager: it replaces the ADD with an MLA even when the MUL cannot be eliminated, e.g. when it has another use. An MLA is usually has a higher latency than an ADD (and there are fewer pipes available that can execute it), so trading an MLA for an ADD is not great. ISel is not taking the number of uses of the MUL result into account, nor any other factors such as the length of the critical path or other resource pressure. The MachineCombiner is able to make these judgments so this patch ports the ISel pattern for MUL/ADD fusing to the MachineCombiner. Similarly for MUL/SUB -> MLS, as well as the indexed variants. The change has no impact on SPEC CPU© intrate nor fprate. Reviewers: dmgreen, SjoerdMeijer, fhahn, Gerolf Subscribers: kristof.beyls, hiraditya, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D70673		2019-12-03 15:48:37 +00:00
..
llvm	[AArch64] Fix over-eager fusing of NEON SIMD MUL/ADD	2019-12-03 15:48:37 +00:00
llvm-c	Recommit "[DWARF5]Addition of alignment atrribute in typedef DIE."	2019-12-03 09:51:43 +05:30