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llvm-mirror/test/CodeGen/MIR
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Tom Stellard eeebdabf5d AMDGPU/SI: Handle s_getreg hazard in GCNHazardRecognizer 
Reviewers: arsenm

Subscribers: kzhuravl, wdng, nhaehnle, yaxunl, llvm-commits, tony-tye

Differential Revision: https://reviews.llvm.org/D25526

llvm-svn: 284298
2016-10-15 00:58:14 +00:00
..
AArch64 Add AArch64 unit tests 2016-10-12 09:00:44 +00:00
AMDGPU AMDGPU/SI: Handle s_getreg hazard in GCNHazardRecognizer 2016-10-15 00:58:14 +00:00
ARM MachineFunctionProperties/MIRParser: Rename AllVRegsAllocated->NoVRegs, compute it 2016-08-25 01:27:13 +00:00
Generic MIRParser/MIRPrinter: Compute HasInlineAsm instead of printing/parsing it 2016-08-24 22:34:06 +00:00
Hexagon [MIRParser] Parse lane masks for register live-ins 2016-10-12 21:06:45 +00:00
Lanai MachineFunctionProperties/MIRParser: Rename AllVRegsAllocated->NoVRegs, compute it 2016-08-25 01:27:13 +00:00
Mips MIRParser: Use shorter cfi identifiers 2016-07-26 18:20:00 +00:00
NVPTX llc: Add support for -run-pass none 2016-07-16 02:24:59 +00:00
PowerPC MIRParser/MIRPrinter: Compute isSSA instead of printing/parsing it. 2016-08-24 01:32:41 +00:00
X86 MIRParser: Rewrite register info initialization; mostly NFC 2016-10-11 03:13:01 +00:00