Diana Picus 16203cc75a [ARM] GlobalISel: Support G_XOR ...

Same as the other binary operators:
- legalize to 32 bits
- map to GPRs
- select to EORrr via TableGen'erated code

llvm-svn: 304898

2017-06-07 11:57:30 +00:00

..

AArch64

[Improve CodeGen Testing] This patch renables MIRPrinter print fields which have value equal to its default.

2017-06-06 08:16:19 +00:00

AMDGPU

AMDGPU/GlobalISel: Mark 32-bit G_ICMP as legal

2017-06-06 14:16:50 +00:00

ARM

[ARM] GlobalISel: Support G_XOR

2017-06-07 11:57:30 +00:00

AVR

[AVR] Fix a big in shift operator lowering; Authored by Dr. Gergo Erdi

2017-05-31 06:27:46 +00:00

BPF

[bpf] fix a bug which causes incorrect big endian reloc fixup

2017-05-05 18:05:00 +00:00

Generic

CodeGen/LLVMTargetMachine: Refactor ISel pass construction; NFCI

2017-06-06 00:26:13 +00:00

Hexagon

[Hexagon] Return 0 from getDotNewPredOp when .new opcode does not exist

2017-06-02 14:07:06 +00:00

Inputs

…

Lanai

CodeGen: Rename DEBUG_TYPE to match passnames

2017-05-25 21:26:32 +00:00

Mips

evert "[mips] Fix test mips64fpldst.ll with machine verifier enabled"

2017-06-07 11:21:37 +00:00

MIR

llc: Add ability to parse mir from stdin

2017-06-06 20:06:57 +00:00

MSP430

[MSP430] Fix PR33050: Don't use ADD16ri to lower FrameIndex.

2017-05-24 15:08:30 +00:00

Nios2

[Nios2] Target registration

2017-05-29 09:48:30 +00:00

NVPTX

Revert r302938 "Add LiveRangeShrink pass to shrink live range within BB."

2017-05-18 18:50:05 +00:00

PowerPC

[CGP / PowerPC] use direct compares if there's only one load per block in memcmp() expansion

2017-06-07 00:17:08 +00:00

SPARC

Revert r302938 "Add LiveRangeShrink pass to shrink live range within BB."

2017-05-18 18:50:05 +00:00

SystemZ

[SystemZ] Simplify test case. NFC

2017-06-02 23:40:58 +00:00

Thumb

Move machine-cse-physreg.mir to test/CodeGen/Thumb

2017-05-24 17:20:47 +00:00

Thumb2

MIR: remove explicit "noVRegs" property.

2017-05-30 21:28:57 +00:00

WebAssembly

[wasm] Fix test after r304117.

2017-05-29 16:32:52 +00:00

WinEH

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X86

[X86][SSE] Fix an issue with PEXTRW/PEXTRB indices during shuffle combining

2017-06-07 10:30:35 +00:00

XCore

AsmPrinter: mark the beginning and the end of a function in verbose mode

2017-05-23 21:22:16 +00:00