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6b427f77ee
Implement isLegalToVectorizeLoadChain for AMDGPU to avoid producing private address spaces accesses that will need to be split up later. This was doing the wrong thing in the case where the queried chain was an even number of elements. A possible <4 x i32> store was being split into store <2 x i32> store i32 store i32 rather than store <2 x i32> store <2 x i32> when legal. llvm-svn: 295933
122 lines
4.2 KiB
C++
122 lines
4.2 KiB
C++
//===-- AMDGPUTargetTransformInfo.h - AMDGPU specific TTI -------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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/// \file
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/// This file a TargetTransformInfo::Concept conforming object specific to the
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/// AMDGPU target machine. It uses the target's detailed information to
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/// provide more precise answers to certain TTI queries, while letting the
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/// target independent and default TTI implementations handle the rest.
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///
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_AMDGPU_AMDGPUTARGETTRANSFORMINFO_H
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#define LLVM_LIB_TARGET_AMDGPU_AMDGPUTARGETTRANSFORMINFO_H
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#include "AMDGPU.h"
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#include "AMDGPUTargetMachine.h"
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#include "llvm/Analysis/TargetTransformInfo.h"
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#include "llvm/CodeGen/BasicTTIImpl.h"
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namespace llvm {
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class AMDGPUTargetLowering;
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class AMDGPUTTIImpl final : public BasicTTIImplBase<AMDGPUTTIImpl> {
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typedef BasicTTIImplBase<AMDGPUTTIImpl> BaseT;
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typedef TargetTransformInfo TTI;
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friend BaseT;
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const AMDGPUSubtarget *ST;
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const AMDGPUTargetLowering *TLI;
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bool IsGraphicsShader;
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const AMDGPUSubtarget *getST() const { return ST; }
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const AMDGPUTargetLowering *getTLI() const { return TLI; }
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static inline int getFullRateInstrCost() {
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return TargetTransformInfo::TCC_Basic;
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}
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static inline int getHalfRateInstrCost() {
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return 2 * TargetTransformInfo::TCC_Basic;
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}
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// TODO: The size is usually 8 bytes, but takes 4x as many cycles. Maybe
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// should be 2 or 4.
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static inline int getQuarterRateInstrCost() {
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return 3 * TargetTransformInfo::TCC_Basic;
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}
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// On some parts, normal fp64 operations are half rate, and others
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// quarter. This also applies to some integer operations.
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inline int get64BitInstrCost() const {
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return ST->hasHalfRate64Ops() ?
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getHalfRateInstrCost() : getQuarterRateInstrCost();
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}
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public:
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explicit AMDGPUTTIImpl(const AMDGPUTargetMachine *TM, const Function &F)
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: BaseT(TM, F.getParent()->getDataLayout()),
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ST(TM->getSubtargetImpl(F)),
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TLI(ST->getTargetLowering()),
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IsGraphicsShader(AMDGPU::isShader(F.getCallingConv())) {}
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bool hasBranchDivergence() { return true; }
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void getUnrollingPreferences(Loop *L, TTI::UnrollingPreferences &UP);
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TTI::PopcntSupportKind getPopcntSupport(unsigned TyWidth) {
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assert(isPowerOf2_32(TyWidth) && "Ty width must be power of 2");
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return TTI::PSK_FastHardware;
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}
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unsigned getNumberOfRegisters(bool Vector);
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unsigned getRegisterBitWidth(bool Vector);
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unsigned getLoadStoreVecRegBitWidth(unsigned AddrSpace) const;
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bool isLegalToVectorizeMemChain(unsigned ChainSizeInBytes,
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unsigned Alignment,
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unsigned AddrSpace) const;
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bool isLegalToVectorizeLoadChain(unsigned ChainSizeInBytes,
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unsigned Alignment,
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unsigned AddrSpace) const;
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bool isLegalToVectorizeStoreChain(unsigned ChainSizeInBytes,
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unsigned Alignment,
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unsigned AddrSpace) const;
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unsigned getMaxInterleaveFactor(unsigned VF);
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int getArithmeticInstrCost(
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unsigned Opcode, Type *Ty,
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TTI::OperandValueKind Opd1Info = TTI::OK_AnyValue,
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TTI::OperandValueKind Opd2Info = TTI::OK_AnyValue,
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TTI::OperandValueProperties Opd1PropInfo = TTI::OP_None,
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TTI::OperandValueProperties Opd2PropInfo = TTI::OP_None,
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ArrayRef<const Value *> Args = ArrayRef<const Value *>());
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unsigned getCFInstrCost(unsigned Opcode);
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int getVectorInstrCost(unsigned Opcode, Type *ValTy, unsigned Index);
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bool isSourceOfDivergence(const Value *V) const;
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unsigned getFlatAddressSpace() const {
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// Don't bother running InferAddressSpaces pass on graphics shaders which
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// don't use flat addressing.
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if (IsGraphicsShader)
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return -1;
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return ST->hasFlatAddressSpace() ?
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AMDGPUAS::FLAT_ADDRESS : AMDGPUAS::UNKNOWN_ADDRESS_SPACE;
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}
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unsigned getVectorSplitCost() { return 0; }
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};
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} // end namespace llvm
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#endif
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