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122 lines
3.3 KiB
LLVM
122 lines
3.3 KiB
LLVM
; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
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define <8 x i8> @vnegs8(<8 x i8>* %A) nounwind {
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;CHECK: vnegs8:
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;CHECK: vneg.s8
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%tmp1 = load <8 x i8>* %A
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%tmp2 = sub <8 x i8> zeroinitializer, %tmp1
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ret <8 x i8> %tmp2
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}
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define <4 x i16> @vnegs16(<4 x i16>* %A) nounwind {
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;CHECK: vnegs16:
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;CHECK: vneg.s16
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%tmp1 = load <4 x i16>* %A
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%tmp2 = sub <4 x i16> zeroinitializer, %tmp1
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ret <4 x i16> %tmp2
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}
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define <2 x i32> @vnegs32(<2 x i32>* %A) nounwind {
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;CHECK: vnegs32:
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;CHECK: vneg.s32
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%tmp1 = load <2 x i32>* %A
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%tmp2 = sub <2 x i32> zeroinitializer, %tmp1
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ret <2 x i32> %tmp2
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}
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define <2 x float> @vnegf32(<2 x float>* %A) nounwind {
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;CHECK: vnegf32:
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;CHECK: vneg.f32
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%tmp1 = load <2 x float>* %A
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%tmp2 = sub <2 x float> < float -0.000000e+00, float -0.000000e+00 >, %tmp1
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ret <2 x float> %tmp2
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}
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define <16 x i8> @vnegQs8(<16 x i8>* %A) nounwind {
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;CHECK: vnegQs8:
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;CHECK: vneg.s8
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%tmp1 = load <16 x i8>* %A
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%tmp2 = sub <16 x i8> zeroinitializer, %tmp1
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ret <16 x i8> %tmp2
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}
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define <8 x i16> @vnegQs16(<8 x i16>* %A) nounwind {
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;CHECK: vnegQs16:
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;CHECK: vneg.s16
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%tmp1 = load <8 x i16>* %A
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%tmp2 = sub <8 x i16> zeroinitializer, %tmp1
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ret <8 x i16> %tmp2
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}
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define <4 x i32> @vnegQs32(<4 x i32>* %A) nounwind {
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;CHECK: vnegQs32:
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;CHECK: vneg.s32
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%tmp1 = load <4 x i32>* %A
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%tmp2 = sub <4 x i32> zeroinitializer, %tmp1
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ret <4 x i32> %tmp2
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}
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define <4 x float> @vnegQf32(<4 x float>* %A) nounwind {
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;CHECK: vnegQf32:
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;CHECK: vneg.f32
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%tmp1 = load <4 x float>* %A
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%tmp2 = sub <4 x float> < float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00 >, %tmp1
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ret <4 x float> %tmp2
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}
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define <8 x i8> @vqnegs8(<8 x i8>* %A) nounwind {
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;CHECK: vqnegs8:
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;CHECK: vqneg.s8
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%tmp1 = load <8 x i8>* %A
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%tmp2 = call <8 x i8> @llvm.arm.neon.vqneg.v8i8(<8 x i8> %tmp1)
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ret <8 x i8> %tmp2
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}
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define <4 x i16> @vqnegs16(<4 x i16>* %A) nounwind {
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;CHECK: vqnegs16:
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;CHECK: vqneg.s16
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%tmp1 = load <4 x i16>* %A
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%tmp2 = call <4 x i16> @llvm.arm.neon.vqneg.v4i16(<4 x i16> %tmp1)
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ret <4 x i16> %tmp2
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}
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define <2 x i32> @vqnegs32(<2 x i32>* %A) nounwind {
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;CHECK: vqnegs32:
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;CHECK: vqneg.s32
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%tmp1 = load <2 x i32>* %A
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%tmp2 = call <2 x i32> @llvm.arm.neon.vqneg.v2i32(<2 x i32> %tmp1)
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ret <2 x i32> %tmp2
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}
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define <16 x i8> @vqnegQs8(<16 x i8>* %A) nounwind {
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;CHECK: vqnegQs8:
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;CHECK: vqneg.s8
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%tmp1 = load <16 x i8>* %A
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%tmp2 = call <16 x i8> @llvm.arm.neon.vqneg.v16i8(<16 x i8> %tmp1)
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ret <16 x i8> %tmp2
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}
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define <8 x i16> @vqnegQs16(<8 x i16>* %A) nounwind {
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;CHECK: vqnegQs16:
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;CHECK: vqneg.s16
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%tmp1 = load <8 x i16>* %A
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%tmp2 = call <8 x i16> @llvm.arm.neon.vqneg.v8i16(<8 x i16> %tmp1)
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ret <8 x i16> %tmp2
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}
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define <4 x i32> @vqnegQs32(<4 x i32>* %A) nounwind {
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;CHECK: vqnegQs32:
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;CHECK: vqneg.s32
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%tmp1 = load <4 x i32>* %A
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%tmp2 = call <4 x i32> @llvm.arm.neon.vqneg.v4i32(<4 x i32> %tmp1)
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ret <4 x i32> %tmp2
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}
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declare <8 x i8> @llvm.arm.neon.vqneg.v8i8(<8 x i8>) nounwind readnone
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declare <4 x i16> @llvm.arm.neon.vqneg.v4i16(<4 x i16>) nounwind readnone
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declare <2 x i32> @llvm.arm.neon.vqneg.v2i32(<2 x i32>) nounwind readnone
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declare <16 x i8> @llvm.arm.neon.vqneg.v16i8(<16 x i8>) nounwind readnone
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declare <8 x i16> @llvm.arm.neon.vqneg.v8i16(<8 x i16>) nounwind readnone
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declare <4 x i32> @llvm.arm.neon.vqneg.v4i32(<4 x i32>) nounwind readnone
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