mirror of
https://github.com/RPCS3/llvm-mirror.git
synced 2024-10-26 14:33:02 +02:00
bbc4bbde20
llvm-svn: 253777
820 lines
27 KiB
C++
820 lines
27 KiB
C++
//===-- X86InstComments.cpp - Generate verbose-asm comments for instrs ----===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This defines functionality used to emit comments about X86 instructions to
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// an output stream for -fverbose-asm.
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//
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//===----------------------------------------------------------------------===//
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#include "X86InstComments.h"
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#include "MCTargetDesc/X86MCTargetDesc.h"
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#include "Utils/X86ShuffleDecode.h"
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#include "llvm/MC/MCInst.h"
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#include "llvm/CodeGen/MachineValueType.h"
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#include "llvm/Support/raw_ostream.h"
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using namespace llvm;
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static unsigned getVectorRegSize(unsigned RegNo) {
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if (X86::ZMM0 <= RegNo && RegNo <= X86::ZMM31)
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return 512;
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if (X86::YMM0 <= RegNo && RegNo <= X86::YMM31)
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return 256;
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if (X86::XMM0 <= RegNo && RegNo <= X86::XMM31)
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return 128;
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if (X86::MM0 <= RegNo && RegNo <= X86::MM7)
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return 64;
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llvm_unreachable("Unknown vector reg!");
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return 0;
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}
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static MVT getRegOperandVectorVT(const MCInst *MI, const MVT &ScalarVT,
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unsigned OperandIndex) {
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unsigned OpReg = MI->getOperand(OperandIndex).getReg();
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return MVT::getVectorVT(ScalarVT,
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getVectorRegSize(OpReg)/ScalarVT.getSizeInBits());
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}
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/// \brief Extracts the src/dst types for a given zero extension instruction.
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/// \note While the number of elements in DstVT type correct, the
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/// number in the SrcVT type is expanded to fill the src xmm register and the
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/// upper elements may not be included in the dst xmm/ymm register.
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static void getZeroExtensionTypes(const MCInst *MI, MVT &SrcVT, MVT &DstVT) {
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switch (MI->getOpcode()) {
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default:
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llvm_unreachable("Unknown zero extension instruction");
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// i8 zero extension
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case X86::PMOVZXBWrm:
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case X86::PMOVZXBWrr:
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case X86::VPMOVZXBWrm:
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case X86::VPMOVZXBWrr:
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SrcVT = MVT::v16i8;
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DstVT = MVT::v8i16;
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break;
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case X86::VPMOVZXBWYrm:
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case X86::VPMOVZXBWYrr:
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SrcVT = MVT::v16i8;
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DstVT = MVT::v16i16;
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break;
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case X86::PMOVZXBDrm:
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case X86::PMOVZXBDrr:
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case X86::VPMOVZXBDrm:
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case X86::VPMOVZXBDrr:
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SrcVT = MVT::v16i8;
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DstVT = MVT::v4i32;
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break;
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case X86::VPMOVZXBDYrm:
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case X86::VPMOVZXBDYrr:
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SrcVT = MVT::v16i8;
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DstVT = MVT::v8i32;
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break;
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case X86::PMOVZXBQrm:
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case X86::PMOVZXBQrr:
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case X86::VPMOVZXBQrm:
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case X86::VPMOVZXBQrr:
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SrcVT = MVT::v16i8;
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DstVT = MVT::v2i64;
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break;
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case X86::VPMOVZXBQYrm:
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case X86::VPMOVZXBQYrr:
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SrcVT = MVT::v16i8;
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DstVT = MVT::v4i64;
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break;
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// i16 zero extension
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case X86::PMOVZXWDrm:
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case X86::PMOVZXWDrr:
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case X86::VPMOVZXWDrm:
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case X86::VPMOVZXWDrr:
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SrcVT = MVT::v8i16;
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DstVT = MVT::v4i32;
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break;
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case X86::VPMOVZXWDYrm:
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case X86::VPMOVZXWDYrr:
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SrcVT = MVT::v8i16;
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DstVT = MVT::v8i32;
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break;
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case X86::PMOVZXWQrm:
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case X86::PMOVZXWQrr:
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case X86::VPMOVZXWQrm:
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case X86::VPMOVZXWQrr:
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SrcVT = MVT::v8i16;
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DstVT = MVT::v2i64;
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break;
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case X86::VPMOVZXWQYrm:
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case X86::VPMOVZXWQYrr:
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SrcVT = MVT::v8i16;
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DstVT = MVT::v4i64;
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break;
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// i32 zero extension
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case X86::PMOVZXDQrm:
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case X86::PMOVZXDQrr:
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case X86::VPMOVZXDQrm:
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case X86::VPMOVZXDQrr:
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SrcVT = MVT::v4i32;
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DstVT = MVT::v2i64;
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break;
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case X86::VPMOVZXDQYrm:
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case X86::VPMOVZXDQYrr:
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SrcVT = MVT::v4i32;
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DstVT = MVT::v4i64;
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break;
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}
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}
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#define CASE_MASK_INS_COMMON(Inst, Suffix, src) \
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case X86::V##Inst##Suffix##src: \
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case X86::V##Inst##Suffix##src##k: \
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case X86::V##Inst##Suffix##src##kz:
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#define CASE_SSE_INS_COMMON(Inst, src) \
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case X86::Inst##src:
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#define CASE_AVX_INS_COMMON(Inst, Suffix, src) \
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case X86::V##Inst##Suffix##src:
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#define CASE_MOVDUP(Inst, src) \
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CASE_MASK_INS_COMMON(Inst, Z, r##src) \
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CASE_MASK_INS_COMMON(Inst, Z256, r##src) \
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CASE_MASK_INS_COMMON(Inst, Z128, r##src) \
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CASE_AVX_INS_COMMON(Inst, , r##src) \
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CASE_AVX_INS_COMMON(Inst, Y, r##src) \
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CASE_SSE_INS_COMMON(Inst, r##src) \
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#define CASE_UNPCK(Inst, src) \
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CASE_MASK_INS_COMMON(Inst, Z, r##src) \
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CASE_MASK_INS_COMMON(Inst, Z256, r##src) \
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CASE_MASK_INS_COMMON(Inst, Z128, r##src) \
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CASE_AVX_INS_COMMON(Inst, , r##src) \
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CASE_AVX_INS_COMMON(Inst, Y, r##src) \
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CASE_SSE_INS_COMMON(Inst, r##src) \
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#define CASE_SHUF(Inst, src) \
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CASE_MASK_INS_COMMON(Inst, Z, r##src##i) \
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CASE_MASK_INS_COMMON(Inst, Z256, r##src##i) \
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CASE_MASK_INS_COMMON(Inst, Z128, r##src##i) \
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CASE_AVX_INS_COMMON(Inst, , r##src##i) \
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CASE_AVX_INS_COMMON(Inst, Y, r##src##i) \
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CASE_SSE_INS_COMMON(Inst, r##src##i) \
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#define CASE_VPERM(Inst, src) \
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CASE_MASK_INS_COMMON(Inst, Z, src##i) \
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CASE_MASK_INS_COMMON(Inst, Z256, src##i) \
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CASE_MASK_INS_COMMON(Inst, Z128, src##i) \
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CASE_AVX_INS_COMMON(Inst, , src##i) \
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CASE_AVX_INS_COMMON(Inst, Y, src##i) \
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#define CASE_VSHUF(Inst, src) \
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CASE_MASK_INS_COMMON(SHUFF##Inst, Z, r##src##i) \
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CASE_MASK_INS_COMMON(SHUFI##Inst, Z, r##src##i) \
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CASE_MASK_INS_COMMON(SHUFF##Inst, Z256, r##src##i) \
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CASE_MASK_INS_COMMON(SHUFI##Inst, Z256, r##src##i) \
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/// \brief Extracts the types and if it has memory operand for a given
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/// (SHUFF32x4/SHUFF64x2/SHUFI32x4/SHUFI64x2) instruction.
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static void getVSHUF64x2FamilyInfo(const MCInst *MI, MVT &VT, bool &HasMemOp) {
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HasMemOp = false;
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switch (MI->getOpcode()) {
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default:
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llvm_unreachable("Unknown VSHUF64x2 family instructions.");
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break;
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CASE_VSHUF(64X2, m)
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HasMemOp = true; // FALL THROUGH.
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CASE_VSHUF(64X2, r)
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VT = getRegOperandVectorVT(MI, MVT::i64, 0);
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break;
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CASE_VSHUF(32X4, m)
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HasMemOp = true; // FALL THROUGH.
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CASE_VSHUF(32X4, r)
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VT = getRegOperandVectorVT(MI, MVT::i32, 0);
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break;
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}
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}
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//===----------------------------------------------------------------------===//
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// Top Level Entrypoint
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//===----------------------------------------------------------------------===//
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/// EmitAnyX86InstComments - This function decodes x86 instructions and prints
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/// newline terminated strings to the specified string if desired. This
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/// information is shown in disassembly dumps when verbose assembly is enabled.
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bool llvm::EmitAnyX86InstComments(const MCInst *MI, raw_ostream &OS,
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const char *(*getRegName)(unsigned)) {
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// If this is a shuffle operation, the switch should fill in this state.
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SmallVector<int, 8> ShuffleMask;
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const char *DestName = nullptr, *Src1Name = nullptr, *Src2Name = nullptr;
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switch (MI->getOpcode()) {
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default:
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// Not an instruction for which we can decode comments.
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return false;
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case X86::BLENDPDrri:
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case X86::VBLENDPDrri:
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case X86::VBLENDPDYrri:
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Src2Name = getRegName(MI->getOperand(2).getReg());
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// FALL THROUGH.
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case X86::BLENDPDrmi:
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case X86::VBLENDPDrmi:
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case X86::VBLENDPDYrmi:
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if (MI->getOperand(MI->getNumOperands() - 1).isImm())
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DecodeBLENDMask(getRegOperandVectorVT(MI, MVT::f64, 0),
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MI->getOperand(MI->getNumOperands() - 1).getImm(),
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ShuffleMask);
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Src1Name = getRegName(MI->getOperand(1).getReg());
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DestName = getRegName(MI->getOperand(0).getReg());
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break;
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case X86::BLENDPSrri:
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case X86::VBLENDPSrri:
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case X86::VBLENDPSYrri:
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Src2Name = getRegName(MI->getOperand(2).getReg());
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// FALL THROUGH.
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case X86::BLENDPSrmi:
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case X86::VBLENDPSrmi:
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case X86::VBLENDPSYrmi:
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if (MI->getOperand(MI->getNumOperands() - 1).isImm())
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DecodeBLENDMask(getRegOperandVectorVT(MI, MVT::f32, 0),
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MI->getOperand(MI->getNumOperands() - 1).getImm(),
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ShuffleMask);
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Src1Name = getRegName(MI->getOperand(1).getReg());
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DestName = getRegName(MI->getOperand(0).getReg());
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break;
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case X86::PBLENDWrri:
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case X86::VPBLENDWrri:
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case X86::VPBLENDWYrri:
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Src2Name = getRegName(MI->getOperand(2).getReg());
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// FALL THROUGH.
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case X86::PBLENDWrmi:
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case X86::VPBLENDWrmi:
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case X86::VPBLENDWYrmi:
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if (MI->getOperand(MI->getNumOperands() - 1).isImm())
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DecodeBLENDMask(getRegOperandVectorVT(MI, MVT::i16, 0),
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MI->getOperand(MI->getNumOperands() - 1).getImm(),
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ShuffleMask);
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Src1Name = getRegName(MI->getOperand(1).getReg());
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DestName = getRegName(MI->getOperand(0).getReg());
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break;
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case X86::VPBLENDDrri:
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case X86::VPBLENDDYrri:
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Src2Name = getRegName(MI->getOperand(2).getReg());
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// FALL THROUGH.
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case X86::VPBLENDDrmi:
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case X86::VPBLENDDYrmi:
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if (MI->getOperand(MI->getNumOperands() - 1).isImm())
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DecodeBLENDMask(getRegOperandVectorVT(MI, MVT::i32, 0),
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MI->getOperand(MI->getNumOperands() - 1).getImm(),
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ShuffleMask);
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Src1Name = getRegName(MI->getOperand(1).getReg());
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DestName = getRegName(MI->getOperand(0).getReg());
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break;
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case X86::INSERTPSrr:
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case X86::VINSERTPSrr:
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Src2Name = getRegName(MI->getOperand(2).getReg());
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// FALL THROUGH.
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case X86::INSERTPSrm:
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case X86::VINSERTPSrm:
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DestName = getRegName(MI->getOperand(0).getReg());
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Src1Name = getRegName(MI->getOperand(1).getReg());
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if (MI->getOperand(MI->getNumOperands() - 1).isImm())
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DecodeINSERTPSMask(MI->getOperand(MI->getNumOperands() - 1).getImm(),
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ShuffleMask);
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break;
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case X86::MOVLHPSrr:
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case X86::VMOVLHPSrr:
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case X86::VMOVLHPSZrr:
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Src2Name = getRegName(MI->getOperand(2).getReg());
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Src1Name = getRegName(MI->getOperand(1).getReg());
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DestName = getRegName(MI->getOperand(0).getReg());
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DecodeMOVLHPSMask(2, ShuffleMask);
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break;
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case X86::MOVHLPSrr:
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case X86::VMOVHLPSrr:
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case X86::VMOVHLPSZrr:
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Src2Name = getRegName(MI->getOperand(2).getReg());
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Src1Name = getRegName(MI->getOperand(1).getReg());
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DestName = getRegName(MI->getOperand(0).getReg());
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DecodeMOVHLPSMask(2, ShuffleMask);
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break;
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CASE_MOVDUP(MOVSLDUP, r)
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Src1Name = getRegName(MI->getOperand(MI->getNumOperands() - 1).getReg());
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// FALL THROUGH.
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CASE_MOVDUP(MOVSLDUP, m)
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DestName = getRegName(MI->getOperand(0).getReg());
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DecodeMOVSLDUPMask(getRegOperandVectorVT(MI, MVT::f32, 0), ShuffleMask);
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break;
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CASE_MOVDUP(MOVSHDUP, r)
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Src1Name = getRegName(MI->getOperand(MI->getNumOperands() - 1).getReg());
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// FALL THROUGH.
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CASE_MOVDUP(MOVSHDUP, m)
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DestName = getRegName(MI->getOperand(0).getReg());
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DecodeMOVSHDUPMask(getRegOperandVectorVT(MI, MVT::f32, 0), ShuffleMask);
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break;
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CASE_MOVDUP(MOVDDUP, r)
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Src1Name = getRegName(MI->getOperand(MI->getNumOperands() - 1).getReg());
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// FALL THROUGH.
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CASE_MOVDUP(MOVDDUP, m)
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DestName = getRegName(MI->getOperand(0).getReg());
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DecodeMOVDDUPMask(getRegOperandVectorVT(MI, MVT::f64, 0), ShuffleMask);
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break;
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case X86::PSLLDQri:
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case X86::VPSLLDQri:
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case X86::VPSLLDQYri:
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Src1Name = getRegName(MI->getOperand(1).getReg());
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DestName = getRegName(MI->getOperand(0).getReg());
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if (MI->getOperand(MI->getNumOperands() - 1).isImm())
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DecodePSLLDQMask(getRegOperandVectorVT(MI, MVT::i8, 0),
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MI->getOperand(MI->getNumOperands() - 1).getImm(),
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ShuffleMask);
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break;
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case X86::PSRLDQri:
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case X86::VPSRLDQri:
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case X86::VPSRLDQYri:
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Src1Name = getRegName(MI->getOperand(1).getReg());
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DestName = getRegName(MI->getOperand(0).getReg());
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if (MI->getOperand(MI->getNumOperands() - 1).isImm())
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DecodePSRLDQMask(getRegOperandVectorVT(MI, MVT::i8, 0),
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MI->getOperand(MI->getNumOperands() - 1).getImm(),
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ShuffleMask);
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break;
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case X86::PALIGNR128rr:
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case X86::VPALIGNR128rr:
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case X86::VPALIGNR256rr:
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Src1Name = getRegName(MI->getOperand(2).getReg());
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// FALL THROUGH.
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case X86::PALIGNR128rm:
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case X86::VPALIGNR128rm:
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case X86::VPALIGNR256rm:
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Src2Name = getRegName(MI->getOperand(1).getReg());
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DestName = getRegName(MI->getOperand(0).getReg());
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if (MI->getOperand(MI->getNumOperands() - 1).isImm())
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DecodePALIGNRMask(getRegOperandVectorVT(MI, MVT::i8, 0),
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MI->getOperand(MI->getNumOperands() - 1).getImm(),
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ShuffleMask);
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break;
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case X86::PSHUFDri:
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case X86::VPSHUFDri:
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case X86::VPSHUFDYri:
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Src1Name = getRegName(MI->getOperand(1).getReg());
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// FALL THROUGH.
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case X86::PSHUFDmi:
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case X86::VPSHUFDmi:
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case X86::VPSHUFDYmi:
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DestName = getRegName(MI->getOperand(0).getReg());
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if (MI->getOperand(MI->getNumOperands() - 1).isImm())
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DecodePSHUFMask(getRegOperandVectorVT(MI, MVT::i32, 0),
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MI->getOperand(MI->getNumOperands() - 1).getImm(),
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ShuffleMask);
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break;
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case X86::PSHUFHWri:
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case X86::VPSHUFHWri:
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case X86::VPSHUFHWYri:
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Src1Name = getRegName(MI->getOperand(1).getReg());
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// FALL THROUGH.
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case X86::PSHUFHWmi:
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case X86::VPSHUFHWmi:
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case X86::VPSHUFHWYmi:
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DestName = getRegName(MI->getOperand(0).getReg());
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if (MI->getOperand(MI->getNumOperands() - 1).isImm())
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DecodePSHUFHWMask(getRegOperandVectorVT(MI, MVT::i16, 0),
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MI->getOperand(MI->getNumOperands() - 1).getImm(),
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ShuffleMask);
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break;
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case X86::PSHUFLWri:
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case X86::VPSHUFLWri:
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case X86::VPSHUFLWYri:
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Src1Name = getRegName(MI->getOperand(1).getReg());
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// FALL THROUGH.
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case X86::PSHUFLWmi:
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case X86::VPSHUFLWmi:
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case X86::VPSHUFLWYmi:
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DestName = getRegName(MI->getOperand(0).getReg());
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if (MI->getOperand(MI->getNumOperands() - 1).isImm())
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DecodePSHUFLWMask(getRegOperandVectorVT(MI, MVT::i16, 0),
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MI->getOperand(MI->getNumOperands() - 1).getImm(),
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ShuffleMask);
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break;
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case X86::MMX_PSHUFWri:
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Src1Name = getRegName(MI->getOperand(1).getReg());
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|
// FALL THROUGH.
|
|
case X86::MMX_PSHUFWmi:
|
|
DestName = getRegName(MI->getOperand(0).getReg());
|
|
if (MI->getOperand(MI->getNumOperands() - 1).isImm())
|
|
DecodePSHUFMask(MVT::v4i16,
|
|
MI->getOperand(MI->getNumOperands() - 1).getImm(),
|
|
ShuffleMask);
|
|
break;
|
|
|
|
case X86::PSWAPDrr:
|
|
Src1Name = getRegName(MI->getOperand(1).getReg());
|
|
// FALL THROUGH.
|
|
case X86::PSWAPDrm:
|
|
DestName = getRegName(MI->getOperand(0).getReg());
|
|
DecodePSWAPMask(MVT::v2i32, ShuffleMask);
|
|
break;
|
|
|
|
CASE_UNPCK(PUNPCKHBW, r)
|
|
case X86::MMX_PUNPCKHBWirr:
|
|
Src2Name = getRegName(MI->getOperand(2).getReg());
|
|
// FALL THROUGH.
|
|
CASE_UNPCK(PUNPCKHBW, m)
|
|
case X86::MMX_PUNPCKHBWirm:
|
|
Src1Name = getRegName(MI->getOperand(1).getReg());
|
|
DestName = getRegName(MI->getOperand(0).getReg());
|
|
DecodeUNPCKHMask(getRegOperandVectorVT(MI, MVT::i8, 0), ShuffleMask);
|
|
break;
|
|
|
|
CASE_UNPCK(PUNPCKHWD, r)
|
|
case X86::MMX_PUNPCKHWDirr:
|
|
Src2Name = getRegName(MI->getOperand(2).getReg());
|
|
// FALL THROUGH.
|
|
CASE_UNPCK(PUNPCKHWD, m)
|
|
case X86::MMX_PUNPCKHWDirm:
|
|
Src1Name = getRegName(MI->getOperand(1).getReg());
|
|
DestName = getRegName(MI->getOperand(0).getReg());
|
|
DecodeUNPCKHMask(getRegOperandVectorVT(MI, MVT::i16, 0), ShuffleMask);
|
|
break;
|
|
|
|
CASE_UNPCK(PUNPCKHDQ, r)
|
|
case X86::MMX_PUNPCKHDQirr:
|
|
Src2Name = getRegName(MI->getOperand(2).getReg());
|
|
// FALL THROUGH.
|
|
CASE_UNPCK(PUNPCKHDQ, m)
|
|
case X86::MMX_PUNPCKHDQirm:
|
|
Src1Name = getRegName(MI->getOperand(1).getReg());
|
|
DestName = getRegName(MI->getOperand(0).getReg());
|
|
DecodeUNPCKHMask(getRegOperandVectorVT(MI, MVT::i32, 0), ShuffleMask);
|
|
break;
|
|
|
|
CASE_UNPCK(PUNPCKHQDQ, r)
|
|
Src2Name = getRegName(MI->getOperand(2).getReg());
|
|
// FALL THROUGH.
|
|
CASE_UNPCK(PUNPCKHQDQ, m)
|
|
Src1Name = getRegName(MI->getOperand(1).getReg());
|
|
DestName = getRegName(MI->getOperand(0).getReg());
|
|
DecodeUNPCKHMask(getRegOperandVectorVT(MI, MVT::i64, 0), ShuffleMask);
|
|
break;
|
|
|
|
CASE_UNPCK(PUNPCKLBW, r)
|
|
case X86::MMX_PUNPCKLBWirr:
|
|
Src2Name = getRegName(MI->getOperand(2).getReg());
|
|
// FALL THROUGH.
|
|
CASE_UNPCK(PUNPCKLBW, m)
|
|
case X86::MMX_PUNPCKLBWirm:
|
|
Src1Name = getRegName(MI->getOperand(1).getReg());
|
|
DestName = getRegName(MI->getOperand(0).getReg());
|
|
DecodeUNPCKLMask(getRegOperandVectorVT(MI, MVT::i8, 0), ShuffleMask);
|
|
break;
|
|
|
|
CASE_UNPCK(PUNPCKLWD, r)
|
|
case X86::MMX_PUNPCKLWDirr:
|
|
Src2Name = getRegName(MI->getOperand(2).getReg());
|
|
// FALL THROUGH.
|
|
CASE_UNPCK(PUNPCKLWD, m)
|
|
case X86::MMX_PUNPCKLWDirm:
|
|
Src1Name = getRegName(MI->getOperand(1).getReg());
|
|
DestName = getRegName(MI->getOperand(0).getReg());
|
|
DecodeUNPCKLMask(getRegOperandVectorVT(MI, MVT::i16, 0), ShuffleMask);
|
|
break;
|
|
|
|
CASE_UNPCK(PUNPCKLDQ, r)
|
|
case X86::MMX_PUNPCKLDQirr:
|
|
Src2Name = getRegName(MI->getOperand(2).getReg());
|
|
// FALL THROUGH.
|
|
CASE_UNPCK(PUNPCKLDQ, m)
|
|
case X86::MMX_PUNPCKLDQirm:
|
|
Src1Name = getRegName(MI->getOperand(1).getReg());
|
|
DestName = getRegName(MI->getOperand(0).getReg());
|
|
DecodeUNPCKLMask(getRegOperandVectorVT(MI, MVT::i32, 0), ShuffleMask);
|
|
break;
|
|
|
|
CASE_UNPCK(PUNPCKLQDQ, r)
|
|
Src2Name = getRegName(MI->getOperand(2).getReg());
|
|
// FALL THROUGH.
|
|
CASE_UNPCK(PUNPCKLQDQ, m)
|
|
Src1Name = getRegName(MI->getOperand(1).getReg());
|
|
DestName = getRegName(MI->getOperand(0).getReg());
|
|
DecodeUNPCKLMask(getRegOperandVectorVT(MI, MVT::i64, 0), ShuffleMask);
|
|
break;
|
|
|
|
CASE_SHUF(SHUFPD, r)
|
|
Src2Name = getRegName(MI->getOperand(2).getReg());
|
|
// FALL THROUGH.
|
|
CASE_SHUF(SHUFPD, m)
|
|
if (MI->getOperand(MI->getNumOperands() - 1).isImm())
|
|
DecodeSHUFPMask(getRegOperandVectorVT(MI, MVT::f64, 0),
|
|
MI->getOperand(MI->getNumOperands() - 1).getImm(),
|
|
ShuffleMask);
|
|
Src1Name = getRegName(MI->getOperand(1).getReg());
|
|
DestName = getRegName(MI->getOperand(0).getReg());
|
|
break;
|
|
|
|
CASE_SHUF(SHUFPS, r)
|
|
Src2Name = getRegName(MI->getOperand(2).getReg());
|
|
// FALL THROUGH.
|
|
CASE_SHUF(SHUFPS, m)
|
|
if (MI->getOperand(MI->getNumOperands() - 1).isImm())
|
|
DecodeSHUFPMask(getRegOperandVectorVT(MI, MVT::f32, 0),
|
|
MI->getOperand(MI->getNumOperands() - 1).getImm(),
|
|
ShuffleMask);
|
|
Src1Name = getRegName(MI->getOperand(1).getReg());
|
|
DestName = getRegName(MI->getOperand(0).getReg());
|
|
break;
|
|
|
|
CASE_VSHUF(64X2, r)
|
|
CASE_VSHUF(64X2, m)
|
|
CASE_VSHUF(32X4, r)
|
|
CASE_VSHUF(32X4, m) {
|
|
MVT VT;
|
|
bool HasMemOp;
|
|
unsigned NumOp = MI->getNumOperands();
|
|
getVSHUF64x2FamilyInfo(MI, VT, HasMemOp);
|
|
decodeVSHUF64x2FamilyMask(VT, MI->getOperand(NumOp - 1).getImm(),
|
|
ShuffleMask);
|
|
DestName = getRegName(MI->getOperand(0).getReg());
|
|
if (HasMemOp) {
|
|
assert((NumOp >= 8) && "Expected at least 8 operands!");
|
|
Src1Name = getRegName(MI->getOperand(NumOp - 7).getReg());
|
|
} else {
|
|
assert((NumOp >= 4) && "Expected at least 4 operands!");
|
|
Src2Name = getRegName(MI->getOperand(NumOp - 2).getReg());
|
|
Src1Name = getRegName(MI->getOperand(NumOp - 3).getReg());
|
|
}
|
|
break;
|
|
}
|
|
|
|
CASE_UNPCK(UNPCKLPD, r)
|
|
Src2Name = getRegName(MI->getOperand(2).getReg());
|
|
// FALL THROUGH.
|
|
CASE_UNPCK(UNPCKLPD, m)
|
|
DecodeUNPCKLMask(getRegOperandVectorVT(MI, MVT::f64, 0), ShuffleMask);
|
|
Src1Name = getRegName(MI->getOperand(1).getReg());
|
|
DestName = getRegName(MI->getOperand(0).getReg());
|
|
break;
|
|
|
|
CASE_UNPCK(UNPCKLPS, r)
|
|
Src2Name = getRegName(MI->getOperand(2).getReg());
|
|
// FALL THROUGH.
|
|
CASE_UNPCK(UNPCKLPS, m)
|
|
DecodeUNPCKLMask(getRegOperandVectorVT(MI, MVT::f32, 0), ShuffleMask);
|
|
Src1Name = getRegName(MI->getOperand(1).getReg());
|
|
DestName = getRegName(MI->getOperand(0).getReg());
|
|
break;
|
|
|
|
CASE_UNPCK(UNPCKHPD, r)
|
|
Src2Name = getRegName(MI->getOperand(2).getReg());
|
|
// FALL THROUGH.
|
|
CASE_UNPCK(UNPCKHPD, m)
|
|
DecodeUNPCKHMask(getRegOperandVectorVT(MI, MVT::f64, 0), ShuffleMask);
|
|
Src1Name = getRegName(MI->getOperand(1).getReg());
|
|
DestName = getRegName(MI->getOperand(0).getReg());
|
|
break;
|
|
|
|
CASE_UNPCK(UNPCKHPS, r)
|
|
Src2Name = getRegName(MI->getOperand(2).getReg());
|
|
// FALL THROUGH.
|
|
CASE_UNPCK(UNPCKHPS, m)
|
|
DecodeUNPCKHMask(getRegOperandVectorVT(MI, MVT::f32, 0), ShuffleMask);
|
|
Src1Name = getRegName(MI->getOperand(1).getReg());
|
|
DestName = getRegName(MI->getOperand(0).getReg());
|
|
break;
|
|
|
|
CASE_VPERM(PERMILPS, r)
|
|
Src1Name = getRegName(MI->getOperand(1).getReg());
|
|
// FALL THROUGH.
|
|
CASE_VPERM(PERMILPS, m)
|
|
if (MI->getOperand(MI->getNumOperands() - 1).isImm())
|
|
DecodePSHUFMask(getRegOperandVectorVT(MI, MVT::f32, 0),
|
|
MI->getOperand(MI->getNumOperands() - 1).getImm(),
|
|
ShuffleMask);
|
|
DestName = getRegName(MI->getOperand(0).getReg());
|
|
break;
|
|
|
|
CASE_VPERM(PERMILPD, r)
|
|
Src1Name = getRegName(MI->getOperand(1).getReg());
|
|
// FALL THROUGH.
|
|
CASE_VPERM(PERMILPD, m)
|
|
if (MI->getOperand(MI->getNumOperands() - 1).isImm())
|
|
DecodePSHUFMask(getRegOperandVectorVT(MI, MVT::f64, 0),
|
|
MI->getOperand(MI->getNumOperands() - 1).getImm(),
|
|
ShuffleMask);
|
|
DestName = getRegName(MI->getOperand(0).getReg());
|
|
break;
|
|
|
|
case X86::VPERM2F128rr:
|
|
case X86::VPERM2I128rr:
|
|
Src2Name = getRegName(MI->getOperand(2).getReg());
|
|
// FALL THROUGH.
|
|
case X86::VPERM2F128rm:
|
|
case X86::VPERM2I128rm:
|
|
// For instruction comments purpose, assume the 256-bit vector is v4i64.
|
|
if (MI->getOperand(MI->getNumOperands() - 1).isImm())
|
|
DecodeVPERM2X128Mask(MVT::v4i64,
|
|
MI->getOperand(MI->getNumOperands() - 1).getImm(),
|
|
ShuffleMask);
|
|
Src1Name = getRegName(MI->getOperand(1).getReg());
|
|
DestName = getRegName(MI->getOperand(0).getReg());
|
|
break;
|
|
|
|
case X86::VPERMQYri:
|
|
case X86::VPERMPDYri:
|
|
Src1Name = getRegName(MI->getOperand(1).getReg());
|
|
// FALL THROUGH.
|
|
case X86::VPERMQYmi:
|
|
case X86::VPERMPDYmi:
|
|
if (MI->getOperand(MI->getNumOperands() - 1).isImm())
|
|
DecodeVPERMMask(MI->getOperand(MI->getNumOperands() - 1).getImm(),
|
|
ShuffleMask);
|
|
DestName = getRegName(MI->getOperand(0).getReg());
|
|
break;
|
|
|
|
case X86::MOVSDrr:
|
|
case X86::VMOVSDrr:
|
|
Src2Name = getRegName(MI->getOperand(2).getReg());
|
|
Src1Name = getRegName(MI->getOperand(1).getReg());
|
|
// FALL THROUGH.
|
|
case X86::MOVSDrm:
|
|
case X86::VMOVSDrm:
|
|
DecodeScalarMoveMask(MVT::v2f64, nullptr == Src2Name, ShuffleMask);
|
|
DestName = getRegName(MI->getOperand(0).getReg());
|
|
break;
|
|
|
|
case X86::MOVSSrr:
|
|
case X86::VMOVSSrr:
|
|
Src2Name = getRegName(MI->getOperand(2).getReg());
|
|
Src1Name = getRegName(MI->getOperand(1).getReg());
|
|
// FALL THROUGH.
|
|
case X86::MOVSSrm:
|
|
case X86::VMOVSSrm:
|
|
DecodeScalarMoveMask(MVT::v4f32, nullptr == Src2Name, ShuffleMask);
|
|
DestName = getRegName(MI->getOperand(0).getReg());
|
|
break;
|
|
|
|
case X86::MOVPQI2QIrr:
|
|
case X86::MOVZPQILo2PQIrr:
|
|
case X86::VMOVPQI2QIrr:
|
|
case X86::VMOVZPQILo2PQIrr:
|
|
Src1Name = getRegName(MI->getOperand(1).getReg());
|
|
// FALL THROUGH.
|
|
case X86::MOVQI2PQIrm:
|
|
case X86::MOVZQI2PQIrm:
|
|
case X86::MOVZPQILo2PQIrm:
|
|
case X86::VMOVQI2PQIrm:
|
|
case X86::VMOVZQI2PQIrm:
|
|
case X86::VMOVZPQILo2PQIrm:
|
|
DecodeZeroMoveLowMask(MVT::v2i64, ShuffleMask);
|
|
DestName = getRegName(MI->getOperand(0).getReg());
|
|
break;
|
|
|
|
case X86::MOVDI2PDIrm:
|
|
case X86::VMOVDI2PDIrm:
|
|
DecodeZeroMoveLowMask(MVT::v4i32, ShuffleMask);
|
|
DestName = getRegName(MI->getOperand(0).getReg());
|
|
break;
|
|
|
|
case X86::EXTRQI:
|
|
if (MI->getOperand(2).isImm() &&
|
|
MI->getOperand(3).isImm())
|
|
DecodeEXTRQIMask(MI->getOperand(2).getImm(),
|
|
MI->getOperand(3).getImm(),
|
|
ShuffleMask);
|
|
|
|
DestName = getRegName(MI->getOperand(0).getReg());
|
|
Src1Name = getRegName(MI->getOperand(1).getReg());
|
|
break;
|
|
|
|
case X86::INSERTQI:
|
|
if (MI->getOperand(3).isImm() &&
|
|
MI->getOperand(4).isImm())
|
|
DecodeINSERTQIMask(MI->getOperand(3).getImm(),
|
|
MI->getOperand(4).getImm(),
|
|
ShuffleMask);
|
|
|
|
DestName = getRegName(MI->getOperand(0).getReg());
|
|
Src1Name = getRegName(MI->getOperand(1).getReg());
|
|
Src2Name = getRegName(MI->getOperand(2).getReg());
|
|
break;
|
|
|
|
case X86::PMOVZXBWrr:
|
|
case X86::PMOVZXBDrr:
|
|
case X86::PMOVZXBQrr:
|
|
case X86::PMOVZXWDrr:
|
|
case X86::PMOVZXWQrr:
|
|
case X86::PMOVZXDQrr:
|
|
case X86::VPMOVZXBWrr:
|
|
case X86::VPMOVZXBDrr:
|
|
case X86::VPMOVZXBQrr:
|
|
case X86::VPMOVZXWDrr:
|
|
case X86::VPMOVZXWQrr:
|
|
case X86::VPMOVZXDQrr:
|
|
case X86::VPMOVZXBWYrr:
|
|
case X86::VPMOVZXBDYrr:
|
|
case X86::VPMOVZXBQYrr:
|
|
case X86::VPMOVZXWDYrr:
|
|
case X86::VPMOVZXWQYrr:
|
|
case X86::VPMOVZXDQYrr:
|
|
Src1Name = getRegName(MI->getOperand(1).getReg());
|
|
// FALL THROUGH.
|
|
case X86::PMOVZXBWrm:
|
|
case X86::PMOVZXBDrm:
|
|
case X86::PMOVZXBQrm:
|
|
case X86::PMOVZXWDrm:
|
|
case X86::PMOVZXWQrm:
|
|
case X86::PMOVZXDQrm:
|
|
case X86::VPMOVZXBWrm:
|
|
case X86::VPMOVZXBDrm:
|
|
case X86::VPMOVZXBQrm:
|
|
case X86::VPMOVZXWDrm:
|
|
case X86::VPMOVZXWQrm:
|
|
case X86::VPMOVZXDQrm:
|
|
case X86::VPMOVZXBWYrm:
|
|
case X86::VPMOVZXBDYrm:
|
|
case X86::VPMOVZXBQYrm:
|
|
case X86::VPMOVZXWDYrm:
|
|
case X86::VPMOVZXWQYrm:
|
|
case X86::VPMOVZXDQYrm: {
|
|
MVT SrcVT, DstVT;
|
|
getZeroExtensionTypes(MI, SrcVT, DstVT);
|
|
DecodeZeroExtendMask(SrcVT, DstVT, ShuffleMask);
|
|
DestName = getRegName(MI->getOperand(0).getReg());
|
|
} break;
|
|
}
|
|
|
|
// The only comments we decode are shuffles, so give up if we were unable to
|
|
// decode a shuffle mask.
|
|
if (ShuffleMask.empty())
|
|
return false;
|
|
|
|
if (!DestName) DestName = Src1Name;
|
|
OS << (DestName ? DestName : "mem") << " = ";
|
|
|
|
// If the two sources are the same, canonicalize the input elements to be
|
|
// from the first src so that we get larger element spans.
|
|
if (Src1Name == Src2Name) {
|
|
for (unsigned i = 0, e = ShuffleMask.size(); i != e; ++i) {
|
|
if ((int)ShuffleMask[i] >= 0 && // Not sentinel.
|
|
ShuffleMask[i] >= (int)e) // From second mask.
|
|
ShuffleMask[i] -= e;
|
|
}
|
|
}
|
|
|
|
// The shuffle mask specifies which elements of the src1/src2 fill in the
|
|
// destination, with a few sentinel values. Loop through and print them
|
|
// out.
|
|
for (unsigned i = 0, e = ShuffleMask.size(); i != e; ++i) {
|
|
if (i != 0)
|
|
OS << ',';
|
|
if (ShuffleMask[i] == SM_SentinelZero) {
|
|
OS << "zero";
|
|
continue;
|
|
}
|
|
|
|
// Otherwise, it must come from src1 or src2. Print the span of elements
|
|
// that comes from this src.
|
|
bool isSrc1 = ShuffleMask[i] < (int)ShuffleMask.size();
|
|
const char *SrcName = isSrc1 ? Src1Name : Src2Name;
|
|
OS << (SrcName ? SrcName : "mem") << '[';
|
|
bool IsFirst = true;
|
|
while (i != e && (int)ShuffleMask[i] != SM_SentinelZero &&
|
|
(ShuffleMask[i] < (int)ShuffleMask.size()) == isSrc1) {
|
|
if (!IsFirst)
|
|
OS << ',';
|
|
else
|
|
IsFirst = false;
|
|
if (ShuffleMask[i] == SM_SentinelUndef)
|
|
OS << "u";
|
|
else
|
|
OS << ShuffleMask[i] % ShuffleMask.size();
|
|
++i;
|
|
}
|
|
OS << ']';
|
|
--i; // For loop increments element #.
|
|
}
|
|
//MI->print(OS, 0);
|
|
OS << "\n";
|
|
|
|
// We successfully added a comment to this instruction.
|
|
return true;
|
|
}
|