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81a9bfe915
This switches to the workaround that HSA defaults to for the mesa path. This should be applied to the 4.0 branch. Patch by Vedran Miletić <vedran@miletic.net> llvm-svn: 292982
48 lines
1.6 KiB
LLVM
48 lines
1.6 KiB
LLVM
; RUN: llc -march=amdgcn -mcpu=verde -verify-machineinstrs < %s | FileCheck %s
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; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck %s
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; CHECK-LABEL: {{^}}main:
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;
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; Test for compilation only. This generated an invalid machine instruction
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; by trying to commute the operands of a V_CMP_EQ_i32_e32 instruction, both
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; of which were in SGPRs.
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define amdgpu_vs float @main(i32 %v) {
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main_body:
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%d1 = call float @llvm.SI.load.const(<16 x i8> undef, i32 960)
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%d2 = call float @llvm.SI.load.const(<16 x i8> undef, i32 976)
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br i1 undef, label %ENDIF56, label %IF57
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IF57: ; preds = %ENDIF
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%v.1 = mul i32 %v, 2
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br label %ENDIF56
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ENDIF56: ; preds = %IF57, %ENDIF
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%v.2 = phi i32 [ %v, %main_body ], [ %v.1, %IF57 ]
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%d1.i = bitcast float %d1 to i32
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%cc1 = icmp eq i32 %d1.i, 0
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br i1 %cc1, label %ENDIF59, label %IF60
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IF60: ; preds = %ENDIF56
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%v.3 = mul i32 %v.2, 2
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br label %ENDIF59
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ENDIF59: ; preds = %IF60, %ENDIF56
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%v.4 = phi i32 [ %v.2, %ENDIF56 ], [ %v.3, %IF60 ]
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%d2.i = bitcast float %d2 to i32
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%cc2 = icmp eq i32 %d2.i, 0
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br i1 %cc2, label %ENDIF62, label %IF63
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IF63: ; preds = %ENDIF59
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unreachable
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ENDIF62: ; preds = %ENDIF59
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%r = bitcast i32 %v.4 to float
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ret float %r
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}
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; Function Attrs: nounwind readnone
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declare float @llvm.SI.load.const(<16 x i8>, i32) #0
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attributes #0 = { nounwind readnone }
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attributes #1 = { readnone }
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