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81a9bfe915
This switches to the workaround that HSA defaults to for the mesa path. This should be applied to the 4.0 branch. Patch by Vedran Miletić <vedran@miletic.net> llvm-svn: 292982
183 lines
8.2 KiB
LLVM
183 lines
8.2 KiB
LLVM
; RUN: llc -march=amdgcn -mcpu=tahiti -fp-contract=on -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GCN-STRICTSI %s
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; RUN: llc -march=amdgcn -mcpu=verde -fp-contract=on -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GCN-STRICT,SI %s
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; RUN: llc -march=amdgcn -mcpu=tahiti -fp-contract=fast -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GCN-CONTRACT,SI %s
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; RUN: llc -march=amdgcn -mcpu=verde -fp-contract=fast -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GCN-CONTRACT,SI %s
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; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -fp-contract=on -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GCN-STRICT,VI %s
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; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -fp-contract=fast -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GCN-CONTRACT,VI %s
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; GCN-LABEL: {{^}}fmuladd_f64:
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; GCN: v_fma_f64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\]}}
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define void @fmuladd_f64(double addrspace(1)* %out, double addrspace(1)* %in1,
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double addrspace(1)* %in2, double addrspace(1)* %in3) #0 {
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%r0 = load double, double addrspace(1)* %in1
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%r1 = load double, double addrspace(1)* %in2
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%r2 = load double, double addrspace(1)* %in3
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%r3 = tail call double @llvm.fmuladd.f64(double %r0, double %r1, double %r2)
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store double %r3, double addrspace(1)* %out
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ret void
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}
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; GCN-LABEL: {{^}}fmul_fadd_f64:
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; GCN-CONTRACT: v_fma_f64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\]}}
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; GCN-STRICT: v_mul_f64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\]}}
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; GCN-STRICT: v_add_f64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\]}}
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define void @fmul_fadd_f64(double addrspace(1)* %out, double addrspace(1)* %in1,
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double addrspace(1)* %in2, double addrspace(1)* %in3) #0 {
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%r0 = load double, double addrspace(1)* %in1
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%r1 = load double, double addrspace(1)* %in2
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%r2 = load double, double addrspace(1)* %in3
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%tmp = fmul double %r0, %r1
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%r3 = fadd double %tmp, %r2
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store double %r3, double addrspace(1)* %out
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ret void
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}
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; GCN-LABEL: {{^}}fadd_a_a_b_f64:
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; GCN: {{buffer|flat}}_load_dwordx2 [[R1:v\[[0-9]+:[0-9]+\]]],
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; GCN: {{buffer|flat}}_load_dwordx2 [[R2:v\[[0-9]+:[0-9]+\]]],
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; GCN-STRICT: v_add_f64 [[TMP:v\[[0-9]+:[0-9]+\]]], [[R1]], [[R1]]
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; GCN-STRICT: v_add_f64 [[RESULT:v\[[0-9]+:[0-9]+\]]], [[TMP]], [[R2]]
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; GCN-CONTRACT: v_fma_f64 [[RESULT:v\[[0-9]+:[0-9]+\]]], [[R1]], 2.0, [[R2]]
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; SI: buffer_store_dwordx2 [[RESULT]]
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; VI: flat_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, [[RESULT]]
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define void @fadd_a_a_b_f64(double addrspace(1)* %out,
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double addrspace(1)* %in1,
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double addrspace(1)* %in2) #0 {
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%tid = call i32 @llvm.amdgcn.workitem.id.x() nounwind readnone
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%gep.0 = getelementptr double, double addrspace(1)* %out, i32 %tid
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%gep.1 = getelementptr double, double addrspace(1)* %gep.0, i32 1
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%gep.out = getelementptr double, double addrspace(1)* %out, i32 %tid
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%r0 = load volatile double, double addrspace(1)* %gep.0
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%r1 = load volatile double, double addrspace(1)* %gep.1
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%add.0 = fadd double %r0, %r0
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%add.1 = fadd double %add.0, %r1
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store double %add.1, double addrspace(1)* %gep.out
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ret void
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}
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; GCN-LABEL: {{^}}fadd_b_a_a_f64:
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; GCN: {{buffer|flat}}_load_dwordx2 [[R1:v\[[0-9]+:[0-9]+\]]],
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; GCN: {{buffer|flat}}_load_dwordx2 [[R2:v\[[0-9]+:[0-9]+\]]],
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; GCN-STRICT: v_add_f64 [[TMP:v\[[0-9]+:[0-9]+\]]], [[R1]], [[R1]]
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; GCN-STRICT: v_add_f64 [[RESULT:v\[[0-9]+:[0-9]+\]]], [[R2]], [[TMP]]
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; GCN-CONTRACT: v_fma_f64 [[RESULT:v\[[0-9]+:[0-9]+\]]], [[R1]], 2.0, [[R2]]
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; SI: buffer_store_dwordx2 [[RESULT]]
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; VI: flat_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, [[RESULT]]
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define void @fadd_b_a_a_f64(double addrspace(1)* %out,
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double addrspace(1)* %in1,
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double addrspace(1)* %in2) #0 {
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%tid = call i32 @llvm.amdgcn.workitem.id.x() nounwind readnone
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%gep.0 = getelementptr double, double addrspace(1)* %out, i32 %tid
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%gep.1 = getelementptr double, double addrspace(1)* %gep.0, i32 1
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%gep.out = getelementptr double, double addrspace(1)* %out, i32 %tid
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%r0 = load volatile double, double addrspace(1)* %gep.0
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%r1 = load volatile double, double addrspace(1)* %gep.1
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%add.0 = fadd double %r0, %r0
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%add.1 = fadd double %r1, %add.0
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store double %add.1, double addrspace(1)* %gep.out
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ret void
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}
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; GCN-LABEL: {{^}}mad_sub_f64:
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; GCN-STRICT: v_mul_f64 v{{\[[0-9]+:[0-9]+\]}}, v{{\[[0-9]+:[0-9]+\]}}, v{{\[[0-9]+:[0-9]+\]}}
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; GCN-STRICT: v_add_f64 v{{\[[0-9]+:[0-9]+\]}}, v{{\[[0-9]+:[0-9]+\]}}, -v{{\[[0-9]+:[0-9]+\]}}
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; GCN-CONTRACT: v_fma_f64 v{{\[[0-9]+:[0-9]+\]}}, v{{\[[0-9]+:[0-9]+\]}}, v{{\[[0-9]+:[0-9]+\]}}, -v{{\[[0-9]+:[0-9]+\]}}
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define void @mad_sub_f64(double addrspace(1)* noalias nocapture %out, double addrspace(1)* noalias nocapture readonly %ptr) #1 {
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%tid = tail call i32 @llvm.amdgcn.workitem.id.x() #0
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%tid.ext = sext i32 %tid to i64
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%gep0 = getelementptr double, double addrspace(1)* %ptr, i64 %tid.ext
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%add1 = add i64 %tid.ext, 1
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%gep1 = getelementptr double, double addrspace(1)* %ptr, i64 %add1
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%add2 = add i64 %tid.ext, 2
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%gep2 = getelementptr double, double addrspace(1)* %ptr, i64 %add2
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%outgep = getelementptr double, double addrspace(1)* %out, i64 %tid.ext
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%a = load volatile double, double addrspace(1)* %gep0, align 8
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%b = load volatile double, double addrspace(1)* %gep1, align 8
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%c = load volatile double, double addrspace(1)* %gep2, align 8
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%mul = fmul double %a, %b
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%sub = fsub double %mul, %c
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store double %sub, double addrspace(1)* %outgep, align 8
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ret void
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}
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; GCN-LABEL: {{^}}fadd_a_a_b_f64_fast_add0:
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; GCN-STRICT: v_add_f64
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; GCN-STRICT: v_add_f64
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; GCN-CONTRACT: v_fma_f64
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define void @fadd_a_a_b_f64_fast_add0(double addrspace(1)* %out,
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double addrspace(1)* %in1,
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double addrspace(1)* %in2) #0 {
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%tid = call i32 @llvm.amdgcn.workitem.id.x() nounwind readnone
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%gep.0 = getelementptr double, double addrspace(1)* %out, i32 %tid
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%gep.1 = getelementptr double, double addrspace(1)* %gep.0, i32 1
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%gep.out = getelementptr double, double addrspace(1)* %out, i32 %tid
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%r0 = load volatile double, double addrspace(1)* %gep.0
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%r1 = load volatile double, double addrspace(1)* %gep.1
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%add.0 = fadd fast double %r0, %r0
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%add.1 = fadd double %add.0, %r1
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store double %add.1, double addrspace(1)* %gep.out
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ret void
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}
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; GCN-LABEL: {{^}}fadd_a_a_b_f64_fast_add1:
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; GCN-STRICT: v_add_f64
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; GCN-STRICT: v_add_f64
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; GCN-CONTRACT: v_fma_f64
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define void @fadd_a_a_b_f64_fast_add1(double addrspace(1)* %out,
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double addrspace(1)* %in1,
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double addrspace(1)* %in2) #0 {
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%tid = call i32 @llvm.amdgcn.workitem.id.x() nounwind readnone
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%gep.0 = getelementptr double, double addrspace(1)* %out, i32 %tid
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%gep.1 = getelementptr double, double addrspace(1)* %gep.0, i32 1
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%gep.out = getelementptr double, double addrspace(1)* %out, i32 %tid
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%r0 = load volatile double, double addrspace(1)* %gep.0
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%r1 = load volatile double, double addrspace(1)* %gep.1
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%add.0 = fadd double %r0, %r0
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%add.1 = fadd fast double %add.0, %r1
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store double %add.1, double addrspace(1)* %gep.out
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ret void
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}
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; GCN-LABEL: {{^}}fadd_a_a_b_f64_fast:
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; GCN: v_fma_f64
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define void @fadd_a_a_b_f64_fast(double addrspace(1)* %out,
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double addrspace(1)* %in1,
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double addrspace(1)* %in2) #0 {
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%tid = call i32 @llvm.amdgcn.workitem.id.x() nounwind readnone
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%gep.0 = getelementptr double, double addrspace(1)* %out, i32 %tid
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%gep.1 = getelementptr double, double addrspace(1)* %gep.0, i32 1
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%gep.out = getelementptr double, double addrspace(1)* %out, i32 %tid
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%r0 = load volatile double, double addrspace(1)* %gep.0
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%r1 = load volatile double, double addrspace(1)* %gep.1
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%add.0 = fadd fast double %r0, %r0
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%add.1 = fadd fast double %add.0, %r1
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store double %add.1, double addrspace(1)* %gep.out
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ret void
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}
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declare i32 @llvm.amdgcn.workitem.id.x() #1
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declare double @llvm.fmuladd.f64(double, double, double) #1
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attributes #0 = { nounwind }
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attributes #1 = { nounwind readnone }
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