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9d10d98e8b
If result of 64-bit address loading combines with 32-bit mask, LLVM
tries to optimize the code and remove "redundant" loading of upper
32-bits of the address. It leads to incorrect code on MIPS64 targets.
MIPS backend creates the following chain of commands to load 64-bit
address in the `MipsTargetLowering::getAddrNonPICSym64` method:
```
(add (shl (add (shl (add %highest(sym), %higher(sym)),
16),
%hi(sym)),
16),
%lo(%sym))
```
If the mask presents, LLVM decides to optimize the chain of commands. It
really does not make sense to load upper 32-bits because the 0x0fffffff
mask anyway clears them. After removing redundant commands we get this
chain:
```
(add (shl (%hi(sym), 16), %lo(%sym))
```
There is no patterns matched `(MipsHi (i64 symbol))`. Due a bug in `SYM_32`
predicate definition, backend incorrectly selects a pattern for a 32-bit
symbols and uses the `lui` instruction for loading `%hi(sym)`.
As a result we get incorrect set of instructions with unnecessary 16-bit
left shifting:
```
lui at,0x0
R_MIPS_HI16 foo
dsll at,at,0x10
daddiu at,at,0
R_MIPS_LO16 foo
```
This patch resolves two problems:
- Fix `SYM_32/SYM_64` predicates to prevent selection of patterns dedicated
to 32-bit symbols in case of using N64 ABI.
- Add missed patterns for 64-bit symbols for `%hi/%lo`.
Fix PR42736.
Differential Revision: https://reviews.llvm.org/D66228
llvm-svn: 370268
58 lines
1.8 KiB
LLVM
58 lines
1.8 KiB
LLVM
; RUN: llc -march=mips -mattr=-long-calls %s -o - \
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; RUN: | FileCheck -check-prefix=OFF %s
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; RUN: llc -march=mips -mattr=+long-calls,+noabicalls %s -o - \
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; RUN: | FileCheck -check-prefix=ON32 %s
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; RUN: llc -march=mips -mattr=+long-calls,-noabicalls %s -o - \
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; RUN: | FileCheck -check-prefix=OFF %s
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; RUN: llc -march=mips64 -target-abi n32 -mattr=-long-calls %s -o - \
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; RUN: | FileCheck -check-prefix=OFF %s
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; RUN: llc -march=mips64 -target-abi n32 -mattr=+long-calls,+noabicalls %s -o - \
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; RUN: | FileCheck -check-prefix=ON32 %s
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; RUN: llc -march=mips64 -target-abi n64 -mattr=-long-calls %s -o - \
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; RUN: | FileCheck -check-prefix=OFF %s
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; RUN: llc -march=mips64 -target-abi n64 -mattr=+long-calls,+noabicalls %s -o - \
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; RUN: | FileCheck -check-prefix=ON64 %s
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declare void @callee()
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declare void @llvm.memset.p0i8.i32(i8* nocapture writeonly, i8, i32, i1)
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@val = internal unnamed_addr global [20 x i32] zeroinitializer, align 4
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define void @caller() {
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; Use `jal` instruction with R_MIPS_26 relocation.
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; OFF: jal callee
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; OFF: jal memset
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; Save the `callee` and `memset` addresses in $25 register
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; and use `jalr` for the jumps.
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; ON32: lui $1, %hi(callee)
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; ON32: addiu $25, $1, %lo(callee)
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; ON32: jalr $25
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; ON32: lui $1, %hi(memset)
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; ON32: addiu $25, $1, %lo(memset)
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; ON32: jalr $25
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; ON64: lui $1, %highest(callee)
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; ON64: daddiu $1, $1, %higher(callee)
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; ON64: daddiu $1, $1, %hi(callee)
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; ON64: daddiu $25, $1, %lo(callee)
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; ON64: jalr $25
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; ON64: lui $2, %highest(memset)
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; ON64: daddiu $1, $2, %higher(memset)
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; ON64: dsll $1, $1, 16
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; ON64: daddiu $1, $1, %hi(memset)
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; ON64: dsll $1, $1, 16
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; ON64: daddiu $25, $1, %lo(memset)
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; ON64: jalr $25
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call void @callee()
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call void @llvm.memset.p0i8.i32(i8* align 4 bitcast ([20 x i32]* @val to i8*), i8 0, i32 80, i1 false)
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ret void
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}
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