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mirror of https://github.com/RPCS3/llvm-mirror.git synced 2024-11-25 04:02:41 +01:00
llvm-mirror/test/CodeGen
Dale Johannesen 907ff5a620 When generating a vector the really slow way, via loads
and stores, handle the case where the element size is not
a valid target type correctly (PPC).

llvm-svn: 89521
2009-11-21 00:53:23 +00:00
..
Alpha
ARM Remat VLDRD from constpool. Clean up some instruction property specifications. 2009-11-20 19:57:15 +00:00
Blackfin
CBackend
CellSPU
CPP
Generic Fix PR5558, which was caused by a wrong fix for PR3393 (see commit 63048), 2009-11-20 10:45:10 +00:00
Mips Unbreak test, Bruno please check. 2009-11-19 07:18:49 +00:00
MSP430 Add and-not (bic) patterns. Based heavily on patch by Brian Lucas! 2009-11-08 15:33:12 +00:00
PIC16
PowerPC When generating a vector the really slow way, via loads 2009-11-21 00:53:23 +00:00
SPARC
SystemZ
Thumb More consistent thumb1 asm printing. 2009-11-19 06:57:41 +00:00
Thumb2 Enable hoisting load from constant memories. 2009-11-20 23:31:34 +00:00
X86 Enable hoisting load from constant memories. 2009-11-20 23:31:34 +00:00
XCore Add XCore support for indirectbr / blockaddress. 2009-11-18 23:20:42 +00:00