..
AsmParser
Disassembler
MCTargetDesc
[NFC] Add 'override' keyword where missing in include/ and lib/.
2020-07-14 09:47:29 -07:00
TargetInfo
Utils
AMDGPU.h
AMDGPU.td
AMDGPUAliasAnalysis.cpp
AMDGPUAliasAnalysis.h
AMDGPUAlwaysInlinePass.cpp
AMDGPUAnnotateKernelFeatures.cpp
AMDGPUAnnotateUniformValues.cpp
AMDGPUArgumentUsageInfo.cpp
AMDGPU/GlobalISel: Add types to special inputs
2020-07-06 17:00:55 -04:00
AMDGPUArgumentUsageInfo.h
AMDGPU/GlobalISel: Add types to special inputs
2020-07-06 17:00:55 -04:00
AMDGPUAsmPrinter.cpp
[AMDGPU][CODEGEN] Added support of new inline assembler constraints
2020-07-02 17:20:15 +03:00
AMDGPUAsmPrinter.h
AMDGPUAtomicOptimizer.cpp
AMDGPUCallingConv.td
AMDGPUCallLowering.cpp
GlobalISel: Handle EVT argument lowering correctly
2020-07-07 16:36:14 -04:00
AMDGPUCallLowering.h
AMDGPUCodeGenPrepare.cpp
[AMDGPU] Fix and simplify AMDGPUCodeGenPrepare::expandDivRem32
2020-07-08 19:14:48 +01:00
AMDGPUCombine.td
AMDGPUExportClustering.cpp
AMDGPUExportClustering.h
AMDGPUFeatures.td
AMDGPUFixFunctionBitcasts.cpp
AMDGPUFrameLowering.cpp
AMDGPUFrameLowering.h
AMDGPUGenRegisterBankInfo.def
AMDGPUGISel.td
AMDGPUGlobalISelUtils.cpp
AMDGPUGlobalISelUtils.h
AMDGPUHSAMetadataStreamer.cpp
AMDGPU: Remove .value_type from kernel metadata
2020-07-10 18:16:31 -04:00
AMDGPUHSAMetadataStreamer.h
AMDGPU: Remove .value_type from kernel metadata
2020-07-10 18:16:31 -04:00
AMDGPUInline.cpp
AMDGPUInstrInfo.cpp
AMDGPUInstrInfo.h
AMDGPUInstrInfo.td
AMDGPUInstructions.td
[AMDGPU] Fix and simplify AMDGPUTargetLowering::LowerUDIVREM
2020-07-08 19:14:49 +01:00
AMDGPUInstructionSelector.cpp
[AMDGPU][GlobalISel] Fix subregister index for EXEC register in selectBallot.
2020-07-13 13:35:34 +02:00
AMDGPUInstructionSelector.h
[AMDGPU][GlobalISel] Select llvm.amdgcn.ballot
2020-07-13 12:14:43 +02:00
AMDGPUISelDAGToDAG.cpp
AMDGPUISelLowering.cpp
[AMDGPU] Fix typos in performCtlz_CttzCombine()
2020-07-14 10:18:18 +01:00
AMDGPUISelLowering.h
AMDGPULegalizerInfo.cpp
GlobalISel: Implement widenScalar for saturating add/sub
2020-07-13 14:46:40 -04:00
AMDGPULegalizerInfo.h
AMDGPULibCalls.cpp
[Alignment][NFC] Use proper getter to retrieve alignment from ConstantInt and ConstantSDNode
2020-07-03 08:06:43 +00:00
AMDGPULibFunc.cpp
AMDGPULibFunc.h
AMDGPULowerIntrinsics.cpp
AMDGPULowerKernelArguments.cpp
[Alignment][NFC] Transition and simplify calls to DL::getABITypeAlignment
2020-07-01 14:31:56 +00:00
AMDGPULowerKernelAttributes.cpp
AMDGPUMachineCFGStructurizer.cpp
AMDGPUMachineFunction.cpp
AMDGPUMachineFunction.h
AMDGPUMachineModuleInfo.cpp
AMDGPUMachineModuleInfo.h
AMDGPUMacroFusion.cpp
AMDGPUMacroFusion.h
AMDGPUMCInstLower.cpp
AMDGPUOpenCLEnqueuedBlockLowering.cpp
AMDGPUPerfHintAnalysis.cpp
AMDGPUPerfHintAnalysis.h
AMDGPUPostLegalizerCombiner.cpp
AMDGPUPreLegalizerCombiner.cpp
AMDGPUPrintfRuntimeBinding.cpp
AMDGPUPromoteAlloca.cpp
[AMDGPU] Limit promote alloca to vector with VGPR budget
2020-07-01 15:57:24 -07:00
AMDGPUPropagateAttributes.cpp
AMDGPUPTNote.h
AMDGPURegBankCombiner.cpp
AMDGPURegisterBankInfo.cpp
[AMDGPU][GlobalISel] Select llvm.amdgcn.ballot
2020-07-13 12:14:43 +02:00
AMDGPURegisterBankInfo.h
AMDGPURegisterBanks.td
AMDGPURewriteOutArguments.cpp
AMDGPUSearchableTables.td
AMDGPUSubtarget.cpp
[AMDGPU] Simplify AMDGPUSubtarget::getWavesPerEU. NFC.
2020-07-14 14:20:02 +01:00
AMDGPUSubtarget.h
AMDGPUTargetMachine.cpp
[AMDGPU] Move LowerSwitch pass to CodeGenPrepare.
2020-07-11 16:33:38 +05:30
AMDGPUTargetMachine.h
AMDGPUTargetObjectFile.cpp
AMDGPUTargetObjectFile.h
AMDGPUTargetTransformInfo.cpp
[NFC] Separate Peeling Properties into its own struct (re-land after minor fix)
2020-07-10 18:39:30 +00:00
AMDGPUTargetTransformInfo.h
[NFC] Separate Peeling Properties into its own struct (re-land after minor fix)
2020-07-10 18:39:30 +00:00
AMDGPUUnifyDivergentExitNodes.cpp
DomTree: Remove getRoots() accessor
2020-07-06 21:58:11 +02:00
AMDGPUUnifyMetadata.cpp
AMDILCFGStructurizer.cpp
AMDKernelCodeT.h
BUFInstructions.td
[AMDGPU][GlobalISel] Fix G_AMDGPU_TBUFFER_STORE_FORMAT mapping
2020-07-10 11:32:32 +02:00
CaymanInstructions.td
[AMDGPU] Fix and simplify AMDGPUTargetLowering::LowerUDIVREM
2020-07-08 19:14:49 +01:00
CMakeLists.txt
DSInstructions.td
EvergreenInstructions.td
FLATInstructions.td
GCNDPPCombine.cpp
[AMDGPU] Don't combine DPP if DPP register is used more than once per instruction
2020-07-03 15:08:26 +03:00
GCNHazardRecognizer.cpp
GCNHazardRecognizer.h
GCNILPSched.cpp
GCNIterativeScheduler.cpp
GCNIterativeScheduler.h
GCNMinRegStrategy.cpp
GCNNSAReassign.cpp
GCNProcessors.td
GCNRegBankReassign.cpp
GCNRegPressure.cpp
GCNRegPressure.h
GCNSchedStrategy.cpp
GCNSchedStrategy.h
LLVMBuild.txt
MIMGInstructions.td
R600.td
R600AsmPrinter.cpp
R600AsmPrinter.h
R600ClauseMergePass.cpp
R600ControlFlowFinalizer.cpp
R600Defines.h
R600EmitClauseMarkers.cpp
R600ExpandSpecialInstrs.cpp
R600FrameLowering.cpp
R600FrameLowering.h
R600InstrFormats.td
R600InstrInfo.cpp
R600InstrInfo.h
R600Instructions.td
R600ISelLowering.cpp
R600ISelLowering.h
R600MachineFunctionInfo.cpp
R600MachineFunctionInfo.h
R600MachineScheduler.cpp
R600MachineScheduler.h
R600OpenCLImageTypeLoweringPass.cpp
R600OptimizeVectorRegisters.cpp
AMDGPU: Use Register
2020-06-30 12:13:08 -04:00
R600Packetizer.cpp
R600Processors.td
R600RegisterInfo.cpp
R600RegisterInfo.h
R600RegisterInfo.td
R600Schedule.td
R700Instructions.td
SIAddIMGInit.cpp
SIAnnotateControlFlow.cpp
SIDefines.h
SIFixSGPRCopies.cpp
SIFixupVectorISel.cpp
SIFixVGPRCopies.cpp
SIFoldOperands.cpp
AMDGPU: Clear subreg when folding immediate copies
2020-07-01 13:59:13 -04:00
SIFormMemoryClauses.cpp
SIFrameLowering.cpp
[Alignment][NFC] Migrate MachineFrameInfo::CreateStackObject to Align
2020-07-01 07:28:11 +00:00
SIFrameLowering.h
SIInsertHardClauses.cpp
SIInsertSkips.cpp
[AMDGPU] Insert PS early exit at end of control flow
2020-07-03 14:04:34 +09:00
SIInsertWaitcnts.cpp
SIInstrFormats.td
SIInstrInfo.cpp
AMDGPU: Set more mov flags on V_ACCVGPR_{READ|WRITE}_B32
2020-07-01 18:58:59 -04:00
SIInstrInfo.h
SIInstrInfo.td
SIInstructions.td
[AMDGPU] Fix and simplify AMDGPUTargetLowering::LowerUDIVREM
2020-07-08 19:14:49 +01:00
SIISelLowering.cpp
[NFC] Change isFPPredicate comparison to ignore lower bound
2020-07-10 11:57:20 +01:00
SIISelLowering.h
[AMDGPU] Tweak getTypeLegalizationCost()
2020-07-06 14:07:48 -07:00
SILoadStoreOptimizer.cpp
SILoadStoreOptimizer: add support for GFX10 image instructions
2020-07-08 19:15:46 +01:00
SILowerControlFlow.cpp
[AMDGPU] Insert PS early exit at end of control flow
2020-07-03 14:04:34 +09:00
SILowerI1Copies.cpp
SILowerSGPRSpills.cpp
[Alignment][NFC] Migrate MachineFrameInfo::CreateStackObject to Align
2020-07-01 07:28:11 +00:00
SIMachineFunctionInfo.cpp
[AMDGPU] Spill more than wavesize CSR SGPRs
2020-07-01 07:40:47 +00:00
SIMachineFunctionInfo.h
AMDGPU/GlobalISel: Add types to special inputs
2020-07-06 17:00:55 -04:00
SIMachineScheduler.cpp
SIMachineScheduler.h
SIMemoryLegalizer.cpp
SIModeRegister.cpp
SIOptimizeExecMasking.cpp
SIOptimizeExecMaskingPreRA.cpp
[AMDGPU] Propagate dead flag during pre-RA exec mask optimizations
2020-07-14 12:53:43 +09:00
SIPeepholeSDWA.cpp
SIPostRABundler.cpp
SIPreAllocateWWMRegs.cpp
SIPreEmitPeephole.cpp
[AMDGPU] Moving SI_RETURN_TO_EPILOG handling out of SIInsertSkips.
2020-06-29 20:41:53 +05:30
SIProgramInfo.h
SIRegisterInfo.cpp
AMDGPU: Use Register
2020-06-30 12:13:08 -04:00
SIRegisterInfo.h
SIRegisterInfo.td
SIRemoveShortExecBranches.cpp
SISchedule.td
SIShrinkInstructions.cpp
[AMDGPU] Avoid using s_cmpk when src0 is not register
2020-07-14 09:05:53 +01:00
SIWholeQuadMode.cpp
SMInstructions.td
SOPInstructions.td
VIInstrFormats.td
VOP1Instructions.td
VOP2Instructions.td
VOP3Instructions.td
VOP3PInstructions.td
AMDGPU: Set more mov flags on V_ACCVGPR_{READ|WRITE}_B32
2020-07-01 18:58:59 -04:00
VOPCInstructions.td
VOPInstructions.td
