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53eb610c7c
These are generated and do not need to have the same values. We are defining separate subregs for R600 and GCN but then using AMDGPU subregs on R600. Differential Revision: https://reviews.llvm.org/D74248
286 lines
10 KiB
C++
286 lines
10 KiB
C++
//===- R600ExpandSpecialInstrs.cpp - Expand special instructions ----------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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/// \file
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/// Vector, Reduction, and Cube instructions need to fill the entire instruction
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/// group to work correctly. This pass expands these individual instructions
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/// into several instructions that will completely fill the instruction group.
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//
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//===----------------------------------------------------------------------===//
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#include "AMDGPU.h"
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#include "AMDGPUSubtarget.h"
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#include "R600Defines.h"
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#include "R600InstrInfo.h"
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#include "R600RegisterInfo.h"
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#include "llvm/CodeGen/MachineBasicBlock.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "MCTargetDesc/AMDGPUMCTargetDesc.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/MachineInstr.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineOperand.h"
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#include "llvm/Pass.h"
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#include <cassert>
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#include <cstdint>
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#include <iterator>
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using namespace llvm;
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#define DEBUG_TYPE "r600-expand-special-instrs"
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namespace {
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class R600ExpandSpecialInstrsPass : public MachineFunctionPass {
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private:
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const R600InstrInfo *TII = nullptr;
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void SetFlagInNewMI(MachineInstr *NewMI, const MachineInstr *OldMI,
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unsigned Op);
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public:
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static char ID;
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R600ExpandSpecialInstrsPass() : MachineFunctionPass(ID) {}
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bool runOnMachineFunction(MachineFunction &MF) override;
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StringRef getPassName() const override {
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return "R600 Expand special instructions pass";
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}
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};
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} // end anonymous namespace
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INITIALIZE_PASS_BEGIN(R600ExpandSpecialInstrsPass, DEBUG_TYPE,
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"R600 Expand Special Instrs", false, false)
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INITIALIZE_PASS_END(R600ExpandSpecialInstrsPass, DEBUG_TYPE,
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"R600ExpandSpecialInstrs", false, false)
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char R600ExpandSpecialInstrsPass::ID = 0;
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char &llvm::R600ExpandSpecialInstrsPassID = R600ExpandSpecialInstrsPass::ID;
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FunctionPass *llvm::createR600ExpandSpecialInstrsPass() {
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return new R600ExpandSpecialInstrsPass();
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}
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void R600ExpandSpecialInstrsPass::SetFlagInNewMI(MachineInstr *NewMI,
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const MachineInstr *OldMI, unsigned Op) {
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int OpIdx = TII->getOperandIdx(*OldMI, Op);
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if (OpIdx > -1) {
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uint64_t Val = OldMI->getOperand(OpIdx).getImm();
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TII->setImmOperand(*NewMI, Op, Val);
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}
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}
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bool R600ExpandSpecialInstrsPass::runOnMachineFunction(MachineFunction &MF) {
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const R600Subtarget &ST = MF.getSubtarget<R600Subtarget>();
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TII = ST.getInstrInfo();
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const R600RegisterInfo &TRI = TII->getRegisterInfo();
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for (MachineFunction::iterator BB = MF.begin(), BB_E = MF.end();
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BB != BB_E; ++BB) {
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MachineBasicBlock &MBB = *BB;
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MachineBasicBlock::iterator I = MBB.begin();
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while (I != MBB.end()) {
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MachineInstr &MI = *I;
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I = std::next(I);
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// Expand LDS_*_RET instructions
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if (TII->isLDSRetInstr(MI.getOpcode())) {
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int DstIdx = TII->getOperandIdx(MI.getOpcode(), R600::OpName::dst);
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assert(DstIdx != -1);
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MachineOperand &DstOp = MI.getOperand(DstIdx);
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MachineInstr *Mov = TII->buildMovInstr(&MBB, I,
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DstOp.getReg(), R600::OQAP);
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DstOp.setReg(R600::OQAP);
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int LDSPredSelIdx = TII->getOperandIdx(MI.getOpcode(),
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R600::OpName::pred_sel);
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int MovPredSelIdx = TII->getOperandIdx(Mov->getOpcode(),
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R600::OpName::pred_sel);
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// Copy the pred_sel bit
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Mov->getOperand(MovPredSelIdx).setReg(
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MI.getOperand(LDSPredSelIdx).getReg());
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}
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switch (MI.getOpcode()) {
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default: break;
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// Expand PRED_X to one of the PRED_SET instructions.
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case R600::PRED_X: {
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uint64_t Flags = MI.getOperand(3).getImm();
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// The native opcode used by PRED_X is stored as an immediate in the
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// third operand.
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MachineInstr *PredSet = TII->buildDefaultInstruction(MBB, I,
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MI.getOperand(2).getImm(), // opcode
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MI.getOperand(0).getReg(), // dst
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MI.getOperand(1).getReg(), // src0
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R600::ZERO); // src1
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TII->addFlag(*PredSet, 0, MO_FLAG_MASK);
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if (Flags & MO_FLAG_PUSH) {
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TII->setImmOperand(*PredSet, R600::OpName::update_exec_mask, 1);
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} else {
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TII->setImmOperand(*PredSet, R600::OpName::update_pred, 1);
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}
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MI.eraseFromParent();
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continue;
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}
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case R600::DOT_4: {
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const R600RegisterInfo &TRI = TII->getRegisterInfo();
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Register DstReg = MI.getOperand(0).getReg();
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unsigned DstBase = TRI.getEncodingValue(DstReg) & HW_REG_MASK;
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for (unsigned Chan = 0; Chan < 4; ++Chan) {
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bool Mask = (Chan != TRI.getHWRegChan(DstReg));
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unsigned SubDstReg =
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R600::R600_TReg32RegClass.getRegister((DstBase * 4) + Chan);
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MachineInstr *BMI =
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TII->buildSlotOfVectorInstruction(MBB, &MI, Chan, SubDstReg);
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if (Chan > 0) {
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BMI->bundleWithPred();
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}
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if (Mask) {
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TII->addFlag(*BMI, 0, MO_FLAG_MASK);
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}
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if (Chan != 3)
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TII->addFlag(*BMI, 0, MO_FLAG_NOT_LAST);
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unsigned Opcode = BMI->getOpcode();
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// While not strictly necessary from hw point of view, we force
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// all src operands of a dot4 inst to belong to the same slot.
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Register Src0 =
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BMI->getOperand(TII->getOperandIdx(Opcode, R600::OpName::src0))
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.getReg();
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Register Src1 =
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BMI->getOperand(TII->getOperandIdx(Opcode, R600::OpName::src1))
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.getReg();
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(void) Src0;
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(void) Src1;
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if ((TRI.getEncodingValue(Src0) & 0xff) < 127 &&
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(TRI.getEncodingValue(Src1) & 0xff) < 127)
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assert(TRI.getHWRegChan(Src0) == TRI.getHWRegChan(Src1));
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}
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MI.eraseFromParent();
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continue;
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}
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}
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bool IsReduction = TII->isReductionOp(MI.getOpcode());
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bool IsVector = TII->isVector(MI);
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bool IsCube = TII->isCubeOp(MI.getOpcode());
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if (!IsReduction && !IsVector && !IsCube) {
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continue;
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}
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// Expand the instruction
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//
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// Reduction instructions:
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// T0_X = DP4 T1_XYZW, T2_XYZW
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// becomes:
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// TO_X = DP4 T1_X, T2_X
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// TO_Y (write masked) = DP4 T1_Y, T2_Y
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// TO_Z (write masked) = DP4 T1_Z, T2_Z
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// TO_W (write masked) = DP4 T1_W, T2_W
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//
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// Vector instructions:
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// T0_X = MULLO_INT T1_X, T2_X
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// becomes:
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// T0_X = MULLO_INT T1_X, T2_X
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// T0_Y (write masked) = MULLO_INT T1_X, T2_X
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// T0_Z (write masked) = MULLO_INT T1_X, T2_X
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// T0_W (write masked) = MULLO_INT T1_X, T2_X
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//
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// Cube instructions:
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// T0_XYZW = CUBE T1_XYZW
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// becomes:
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// TO_X = CUBE T1_Z, T1_Y
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// T0_Y = CUBE T1_Z, T1_X
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// T0_Z = CUBE T1_X, T1_Z
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// T0_W = CUBE T1_Y, T1_Z
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for (unsigned Chan = 0; Chan < 4; Chan++) {
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Register DstReg =
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MI.getOperand(TII->getOperandIdx(MI, R600::OpName::dst)).getReg();
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Register Src0 =
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MI.getOperand(TII->getOperandIdx(MI, R600::OpName::src0)).getReg();
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unsigned Src1 = 0;
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// Determine the correct source registers
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if (!IsCube) {
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int Src1Idx = TII->getOperandIdx(MI, R600::OpName::src1);
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if (Src1Idx != -1) {
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Src1 = MI.getOperand(Src1Idx).getReg();
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}
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}
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if (IsReduction) {
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unsigned SubRegIndex = R600RegisterInfo::getSubRegFromChannel(Chan);
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Src0 = TRI.getSubReg(Src0, SubRegIndex);
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Src1 = TRI.getSubReg(Src1, SubRegIndex);
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} else if (IsCube) {
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static const int CubeSrcSwz[] = {2, 2, 0, 1};
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unsigned SubRegIndex0 = R600RegisterInfo::getSubRegFromChannel(CubeSrcSwz[Chan]);
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unsigned SubRegIndex1 = R600RegisterInfo::getSubRegFromChannel(CubeSrcSwz[3 - Chan]);
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Src1 = TRI.getSubReg(Src0, SubRegIndex1);
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Src0 = TRI.getSubReg(Src0, SubRegIndex0);
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}
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// Determine the correct destination registers;
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bool Mask = false;
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bool NotLast = true;
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if (IsCube) {
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unsigned SubRegIndex = R600RegisterInfo::getSubRegFromChannel(Chan);
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DstReg = TRI.getSubReg(DstReg, SubRegIndex);
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} else {
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// Mask the write if the original instruction does not write to
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// the current Channel.
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Mask = (Chan != TRI.getHWRegChan(DstReg));
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unsigned DstBase = TRI.getEncodingValue(DstReg) & HW_REG_MASK;
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DstReg = R600::R600_TReg32RegClass.getRegister((DstBase * 4) + Chan);
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}
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// Set the IsLast bit
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NotLast = (Chan != 3 );
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// Add the new instruction
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unsigned Opcode = MI.getOpcode();
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switch (Opcode) {
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case R600::CUBE_r600_pseudo:
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Opcode = R600::CUBE_r600_real;
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break;
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case R600::CUBE_eg_pseudo:
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Opcode = R600::CUBE_eg_real;
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break;
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default:
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break;
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}
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MachineInstr *NewMI =
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TII->buildDefaultInstruction(MBB, I, Opcode, DstReg, Src0, Src1);
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if (Chan != 0)
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NewMI->bundleWithPred();
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if (Mask) {
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TII->addFlag(*NewMI, 0, MO_FLAG_MASK);
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}
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if (NotLast) {
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TII->addFlag(*NewMI, 0, MO_FLAG_NOT_LAST);
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}
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SetFlagInNewMI(NewMI, &MI, R600::OpName::clamp);
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SetFlagInNewMI(NewMI, &MI, R600::OpName::literal);
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SetFlagInNewMI(NewMI, &MI, R600::OpName::src0_abs);
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SetFlagInNewMI(NewMI, &MI, R600::OpName::src1_abs);
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SetFlagInNewMI(NewMI, &MI, R600::OpName::src0_neg);
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SetFlagInNewMI(NewMI, &MI, R600::OpName::src1_neg);
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}
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MI.eraseFromParent();
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}
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}
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return false;
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}
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