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e0dc000a0d
We want each register to have a canonical type, which means the best place to store this is in MachineRegisterInfo rather than on every MachineInstr that happens to use or define that register. Most changes following from this are pretty simple (you need an MRI anyway if you're going to be doing any transformations, so just check the type there). But legalization doesn't really want to check redundant operands (when, for example, a G_ADD only ever has one type) so I've made use of MCInstrDesc's operand type field to encode these constraints and limit legalization's work. As an added bonus, more validation is possible, both in MachineVerifier and MachineIRBuilder (coming soon). llvm-svn: 281035
13 lines
385 B
LLVM
13 lines
385 B
LLVM
; RUN: llc -march=amdgcn -mcpu=fiji -O0 -stop-after=irtranslator -global-isel %s -o - 2>&1 | FileCheck %s
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; REQUIRES: global-isel
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; This file checks that the translation from llvm IR to generic MachineInstr
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; is correct.
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; Tests for add.
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; CHECK: name: addi32
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; CHECK: {{%[0-9]+}}(s32) = G_ADD
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define i32 @addi32(i32 %arg1, i32 %arg2) {
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%res = add i32 %arg1, %arg2
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ret i32 %res
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}
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