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llvm-mirror/test/TableGen/intrinsic-varargs.td
Krzysztof Parzyszek 450319e8a0 Add new vector types for 512-, 1024- and 2048-bit vectors
Those types are needed to implement instructions for Hexagon Vector
Extensions (HVX): 16x32, 16x64, 32x16, 32x32, 32x64, 64x8, 64x16,
64x32, 128x8, 128x16, 256x8, 512x1, and 1024x1.

llvm-svn: 253978
2015-11-24 13:07:35 +00:00

31 lines
784 B
TableGen

// RUN: llvm-tblgen -gen-intrinsic %s | FileCheck %s
// XFAIL: vg_leak
class IntrinsicProperty;
class ValueType<int size, int value> {
string Namespace = "MVT";
int Size = size;
int Value = value;
}
class LLVMType<ValueType vt> {
ValueType VT = vt;
}
class Intrinsic<string name, list<LLVMType> param_types = []> {
string LLVMName = name;
bit isTarget = 0;
string TargetPrefix = "";
list<LLVMType> RetTypes = [];
list<LLVMType> ParamTypes = param_types;
list<IntrinsicProperty> Properties = [];
}
// isVoid needs to match the definition in ValueTypes.td
def isVoid : ValueType<0, 66>; // Produces no value
def llvm_vararg_ty : LLVMType<isVoid>; // this means vararg here
// CHECK: /* 0 */ 0, 29, 0,
def int_foo : Intrinsic<"llvm.foo", [llvm_vararg_ty]>;