mirror of
https://github.com/RPCS3/llvm-mirror.git
synced 2024-10-20 19:42:54 +02:00
9099fd3422
In addition to the original commit, tighten the condition for when to pad empty functions to COFF Windows. This avoids running into problems when targeting e.g. Win32 AMDGPU, which caused test failures when this was committed initially. llvm-svn: 301047
145 lines
5.3 KiB
C++
145 lines
5.3 KiB
C++
//===-- Thumb1InstrInfo.cpp - Thumb-1 Instruction Information -------------===//
|
|
//
|
|
// The LLVM Compiler Infrastructure
|
|
//
|
|
// This file is distributed under the University of Illinois Open Source
|
|
// License. See LICENSE.TXT for details.
|
|
//
|
|
//===----------------------------------------------------------------------===//
|
|
//
|
|
// This file contains the Thumb-1 implementation of the TargetInstrInfo class.
|
|
//
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
#include "ARMSubtarget.h"
|
|
#include "Thumb1InstrInfo.h"
|
|
#include "llvm/CodeGen/MachineFrameInfo.h"
|
|
#include "llvm/CodeGen/MachineInstrBuilder.h"
|
|
#include "llvm/CodeGen/MachineMemOperand.h"
|
|
#include "llvm/CodeGen/MachineRegisterInfo.h"
|
|
#include "llvm/MC/MCInst.h"
|
|
|
|
using namespace llvm;
|
|
|
|
Thumb1InstrInfo::Thumb1InstrInfo(const ARMSubtarget &STI)
|
|
: ARMBaseInstrInfo(STI), RI() {}
|
|
|
|
/// Return the noop instruction to use for a noop.
|
|
void Thumb1InstrInfo::getNoop(MCInst &NopInst) const {
|
|
NopInst.setOpcode(ARM::tMOVr);
|
|
NopInst.addOperand(MCOperand::createReg(ARM::R8));
|
|
NopInst.addOperand(MCOperand::createReg(ARM::R8));
|
|
NopInst.addOperand(MCOperand::createImm(ARMCC::AL));
|
|
NopInst.addOperand(MCOperand::createReg(0));
|
|
}
|
|
|
|
unsigned Thumb1InstrInfo::getUnindexedOpcode(unsigned Opc) const {
|
|
return 0;
|
|
}
|
|
|
|
void Thumb1InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
|
|
MachineBasicBlock::iterator I,
|
|
const DebugLoc &DL, unsigned DestReg,
|
|
unsigned SrcReg, bool KillSrc) const {
|
|
// Need to check the arch.
|
|
MachineFunction &MF = *MBB.getParent();
|
|
const ARMSubtarget &st = MF.getSubtarget<ARMSubtarget>();
|
|
|
|
assert(ARM::GPRRegClass.contains(DestReg, SrcReg) &&
|
|
"Thumb1 can only copy GPR registers");
|
|
|
|
if (st.hasV6Ops() || ARM::hGPRRegClass.contains(SrcReg)
|
|
|| !ARM::tGPRRegClass.contains(DestReg))
|
|
BuildMI(MBB, I, DL, get(ARM::tMOVr), DestReg)
|
|
.addReg(SrcReg, getKillRegState(KillSrc))
|
|
.add(predOps(ARMCC::AL));
|
|
else {
|
|
// FIXME: Can also use 'mov hi, $src; mov $dst, hi',
|
|
// with hi as either r10 or r11.
|
|
|
|
const TargetRegisterInfo *RegInfo = st.getRegisterInfo();
|
|
if (MBB.computeRegisterLiveness(RegInfo, ARM::CPSR, I)
|
|
== MachineBasicBlock::LQR_Dead) {
|
|
BuildMI(MBB, I, DL, get(ARM::tMOVSr), DestReg)
|
|
.addReg(SrcReg, getKillRegState(KillSrc))
|
|
->addRegisterDead(ARM::CPSR, RegInfo);
|
|
return;
|
|
}
|
|
|
|
// 'MOV lo, lo' is unpredictable on < v6, so use the stack to do it
|
|
BuildMI(MBB, I, DL, get(ARM::tPUSH))
|
|
.add(predOps(ARMCC::AL))
|
|
.addReg(SrcReg, getKillRegState(KillSrc));
|
|
BuildMI(MBB, I, DL, get(ARM::tPOP))
|
|
.add(predOps(ARMCC::AL))
|
|
.addReg(DestReg, getDefRegState(true));
|
|
}
|
|
}
|
|
|
|
void Thumb1InstrInfo::
|
|
storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
|
|
unsigned SrcReg, bool isKill, int FI,
|
|
const TargetRegisterClass *RC,
|
|
const TargetRegisterInfo *TRI) const {
|
|
assert((RC == &ARM::tGPRRegClass ||
|
|
(TargetRegisterInfo::isPhysicalRegister(SrcReg) &&
|
|
isARMLowRegister(SrcReg))) && "Unknown regclass!");
|
|
|
|
if (RC == &ARM::tGPRRegClass ||
|
|
(TargetRegisterInfo::isPhysicalRegister(SrcReg) &&
|
|
isARMLowRegister(SrcReg))) {
|
|
DebugLoc DL;
|
|
if (I != MBB.end()) DL = I->getDebugLoc();
|
|
|
|
MachineFunction &MF = *MBB.getParent();
|
|
MachineFrameInfo &MFI = MF.getFrameInfo();
|
|
MachineMemOperand *MMO = MF.getMachineMemOperand(
|
|
MachinePointerInfo::getFixedStack(MF, FI), MachineMemOperand::MOStore,
|
|
MFI.getObjectSize(FI), MFI.getObjectAlignment(FI));
|
|
BuildMI(MBB, I, DL, get(ARM::tSTRspi))
|
|
.addReg(SrcReg, getKillRegState(isKill))
|
|
.addFrameIndex(FI)
|
|
.addImm(0)
|
|
.addMemOperand(MMO)
|
|
.add(predOps(ARMCC::AL));
|
|
}
|
|
}
|
|
|
|
void Thumb1InstrInfo::
|
|
loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
|
|
unsigned DestReg, int FI,
|
|
const TargetRegisterClass *RC,
|
|
const TargetRegisterInfo *TRI) const {
|
|
assert((RC == &ARM::tGPRRegClass ||
|
|
(TargetRegisterInfo::isPhysicalRegister(DestReg) &&
|
|
isARMLowRegister(DestReg))) && "Unknown regclass!");
|
|
|
|
if (RC == &ARM::tGPRRegClass ||
|
|
(TargetRegisterInfo::isPhysicalRegister(DestReg) &&
|
|
isARMLowRegister(DestReg))) {
|
|
DebugLoc DL;
|
|
if (I != MBB.end()) DL = I->getDebugLoc();
|
|
|
|
MachineFunction &MF = *MBB.getParent();
|
|
MachineFrameInfo &MFI = MF.getFrameInfo();
|
|
MachineMemOperand *MMO = MF.getMachineMemOperand(
|
|
MachinePointerInfo::getFixedStack(MF, FI), MachineMemOperand::MOLoad,
|
|
MFI.getObjectSize(FI), MFI.getObjectAlignment(FI));
|
|
BuildMI(MBB, I, DL, get(ARM::tLDRspi), DestReg)
|
|
.addFrameIndex(FI)
|
|
.addImm(0)
|
|
.addMemOperand(MMO)
|
|
.add(predOps(ARMCC::AL));
|
|
}
|
|
}
|
|
|
|
void Thumb1InstrInfo::expandLoadStackGuard(
|
|
MachineBasicBlock::iterator MI) const {
|
|
MachineFunction &MF = *MI->getParent()->getParent();
|
|
const TargetMachine &TM = MF.getTarget();
|
|
if (TM.isPositionIndependent())
|
|
expandLoadStackGuardBase(MI, ARM::tLDRLIT_ga_pcrel, ARM::tLDRi);
|
|
else
|
|
expandLoadStackGuardBase(MI, ARM::tLDRLIT_ga_abs, ARM::tLDRi);
|
|
}
|