Craig Topper b807b27145 [RISCV] Improve legalization of i32 UADDO/USUBO on RV64. ... The default legalization uses zero extends that require pair of shifts on RISCV. Instead we can take advantage of the fact that unsigned compares work equally well on sign extended inputs. This allows us to use addw/subw and sext.w. Reviewed By: luismarques Differential Revision: https://reviews.llvm.org/D98233		2021-03-15 09:30:23 -07:00
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Analysis	Reland [SCEV] Improve modelling for (null) pointer constants	2021-03-13 16:05:34 +03:00
Assembler
Bindings
Bitcode
BugPoint
CodeGen	[RISCV] Improve legalization of i32 UADDO/USUBO on RV64.	2021-03-15 09:30:23 -07:00
DebugInfo	[Debug-Info] Add names for the debug line prologue.	2021-03-12 04:45:08 +00:00
Demangle
Examples
ExecutionEngine
Feature
FileCheck	[FileCheck] Add support for hex alternate form in FileCheck	2021-03-12 18:14:17 +00:00
Instrumentation	[dfsan] Update shadow-args-zext.ll test	2021-03-12 20:54:02 -08:00
Integer
JitListener
Linker
LTO
MachineVerifier
MC	[AMDGPU] Restrict image_msaa_load to MSAA dimension types	2021-03-12 09:47:24 +09:00
Object
ObjectYAML
Other	Reland [SCEV] Improve modelling for (null) pointer constants	2021-03-13 16:05:34 +03:00
Reduce
SafepointIRVerifier
Support
SymbolRewriter
TableGen
ThinLTO/X86
tools	[PATCH] fix location of test case	2021-03-15 09:34:24 -04:00
Transforms	[InstSimplify] ctlz({signbit} >>u x) --> x	2021-03-15 12:03:35 -04:00
Unit
Verifier
YAMLParser
.clang-format
CMakeLists.txt
lit.cfg.py	[Debugify][OriginalDIMode] Export the report into JSON file	2021-03-11 01:11:13 -08:00
lit.site.cfg.py.in
TestRunner.sh