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6cafbde06f
Implement CACHE and PREF instructions using mapping. Differential Revision: http://reviews.llvm.org/D8893 llvm-svn: 235379
82 lines
3.0 KiB
TableGen
82 lines
3.0 KiB
TableGen
//=- MicroMips32r6InstrInfo.td - MicroMips r6 Instruction Information -*- tablegen -*-=//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file describes microMIPSr6 instructions.
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//
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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//
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// Instruction Encodings
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//
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//===----------------------------------------------------------------------===//
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class BALC_MMR6_ENC : BRANCH_OFF26_FM<0b101101>;
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class BC_MMR6_ENC : BRANCH_OFF26_FM<0b100101>;
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class BITSWAP_MMR6_ENC : POOL32A_BITSWAP_FM_MMR6<0b101100>;
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class CACHE_MMR6_ENC : CACHE_PREF_FM_MMR6<0b001000, 0b0110>;
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class PREF_MMR6_ENC : CACHE_PREF_FM_MMR6<0b011000, 0b0010>;
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//===----------------------------------------------------------------------===//
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//
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// Instruction Descriptions
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//
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//===----------------------------------------------------------------------===//
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class BC_MMR6_DESC_BASE<string instr_asm, DAGOperand opnd>
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: BRANCH_DESC_BASE, MMR6Arch<instr_asm> {
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dag InOperandList = (ins opnd:$offset);
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dag OutOperandList = (outs);
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string AsmString = !strconcat(instr_asm, "\t$offset");
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bit isBarrier = 1;
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}
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class BALC_MMR6_DESC : BC_MMR6_DESC_BASE<"balc", brtarget26> {
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bit isCall = 1;
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list<Register> Defs = [RA];
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}
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class BC_MMR6_DESC : BC_MMR6_DESC_BASE<"bc", brtarget26>;
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class BITSWAP_MMR6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd>
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: MMR6Arch<instr_asm> {
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dag OutOperandList = (outs GPROpnd:$rd);
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dag InOperandList = (ins GPROpnd:$rt);
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string AsmString = !strconcat(instr_asm, "\t$rd, $rt");
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list<dag> Pattern = [];
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}
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class BITSWAP_MMR6_DESC : BITSWAP_MMR6_DESC_BASE<"bitswap", GPR32Opnd>;
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class CACHE_HINT_MMR6_DESC<string instr_asm, Operand MemOpnd,
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RegisterOperand GPROpnd> : MMR6Arch<instr_asm> {
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dag OutOperandList = (outs);
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dag InOperandList = (ins MemOpnd:$addr, uimm5:$hint);
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string AsmString = !strconcat(instr_asm, "\t$hint, $addr");
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list<dag> Pattern = [];
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string DecoderMethod = "DecodeCacheOpMM";
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}
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class CACHE_MMR6_DESC : CACHE_HINT_MMR6_DESC<"cache", mem_mm_12, GPR32Opnd>;
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class PREF_MMR6_DESC : CACHE_HINT_MMR6_DESC<"pref", mem_mm_12, GPR32Opnd>;
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//===----------------------------------------------------------------------===//
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//
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// Instruction Definitions
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//
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//===----------------------------------------------------------------------===//
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let DecoderNamespace = "MicroMips32r6" in {
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def BALC_MMR6 : R6MMR6Rel, BALC_MMR6_ENC, BALC_MMR6_DESC, ISA_MICROMIPS32R6;
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def BC_MMR6 : R6MMR6Rel, BC_MMR6_ENC, BC_MMR6_DESC, ISA_MICROMIPS32R6;
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def BITSWAP_MMR6 : R6MMR6Rel, BITSWAP_MMR6_ENC, BITSWAP_MMR6_DESC,
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ISA_MICROMIPS32R6;
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def CACHE_MMR6 : R6MMR6Rel, CACHE_MMR6_ENC, CACHE_MMR6_DESC, ISA_MICROMIPS32R6;
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def PREF_MMR6 : R6MMR6Rel, PREF_MMR6_ENC, PREF_MMR6_DESC, ISA_MICROMIPS32R6;
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}
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