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f1346a6bd1
There can be muliple patterns that map to the same compressed instruction. Reversing those leads to multiple ways to uncompress an instruction, but its not easily controllable which one will be chosen by the tablegen backend. This patch adds a flag to mark patterns that should only be used for compressing. This allows us to leave one canonical pattern for uncompressing. The obvious benefit of this is getting c.mv to uncompress to the addi patern that is aliased to the mv pseudoinstruction. For the add/and/or/xor/li patterns it just removes some unreachable code from the generated code. Reviewed By: frasercrmck Differential Revision: https://reviews.llvm.org/D94894
102 lines
3.9 KiB
TableGen
102 lines
3.9 KiB
TableGen
// RUN: llvm-tblgen -gen-compress-inst-emitter -I %p/../../include %s | \
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// RUN: FileCheck --check-prefix=COMPRESS %s
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// Check that combining conditions in AssemblerPredicate generates the correct
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// output when using both the (all_of) AND operator, and the (any_of) OR
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// operator in the RISC-V specific instruction compressor.
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include "llvm/Target/Target.td"
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def archInstrInfo : InstrInfo { }
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def archAsmWriter : AsmWriter {
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int PassSubtarget = 1;
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}
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def arch : Target {
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let InstructionSet = archInstrInfo;
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let AssemblyWriters = [archAsmWriter];
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}
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let Namespace = "arch" in {
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def R0 : Register<"r0">;
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}
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def Regs : RegisterClass<"Regs", [i32], 32, (add R0)>;
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class RVInst<int Opc, list<Predicate> Preds> : Instruction {
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let Size = 4;
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let OutOperandList = (outs);
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let InOperandList = (ins Regs:$r);
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field bits<32> Inst;
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let Inst = Opc;
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let AsmString = NAME # " $r";
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field bits<32> SoftFail = 0;
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let Predicates = Preds;
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}
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class RVInst16<int Opc, list<Predicate> Preds> : Instruction {
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let Size = 2;
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let OutOperandList = (outs);
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let InOperandList = (ins Regs:$r);
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field bits<16> Inst;
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let Inst = Opc;
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let AsmString = NAME # " $r";
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field bits<16> SoftFail = 0;
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let Predicates = Preds;
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}
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def AsmCond1 : SubtargetFeature<"cond1", "cond1", "true", "">;
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def AsmCond2a: SubtargetFeature<"cond2a", "cond2a", "true", "">;
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def AsmCond2b: SubtargetFeature<"cond2b", "cond2b", "true", "">;
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def AsmCond3a: SubtargetFeature<"cond3a", "cond3a", "true", "">;
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def AsmCond3b: SubtargetFeature<"cond3b", "cond3b", "true", "">;
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def AsmPred1 : Predicate<"Pred1">, AssemblerPredicate<(all_of AsmCond1)>;
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def AsmPred2 : Predicate<"Pred2">, AssemblerPredicate<(all_of AsmCond2a, AsmCond2b)>;
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def AsmPred3 : Predicate<"Pred3">, AssemblerPredicate<(any_of AsmCond3a, AsmCond3b)>;
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def BigInst : RVInst<1, [AsmPred1]>;
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class CompressPat<dag input, dag output, list<Predicate> predicates> {
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dag Input = input;
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dag Output = output;
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list<Predicate> Predicates = predicates;
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bit isCompressOnly = false;
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}
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// COMPRESS-LABEL: static bool compressInst
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// COMPRESS: case arch::BigInst
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def SmallInst1 : RVInst16<1, []>;
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def : CompressPat<(BigInst Regs:$r), (SmallInst1 Regs:$r), [AsmPred1]>;
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// COMPRESS: if (STI.getFeatureBits()[arch::AsmCond1] &&
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// COMPRESS-NEXT: (MRI.getRegClass(arch::RegsRegClassID).contains(MI.getOperand(0).getReg()))) {
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// COMPRESS-NEXT: // SmallInst1 $r
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def SmallInst2 : RVInst16<2, []>;
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def : CompressPat<(BigInst Regs:$r), (SmallInst2 Regs:$r), [AsmPred2]>;
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// COMPRESS: if (STI.getFeatureBits()[arch::AsmCond2a] &&
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// COMPRESS-NEXT: STI.getFeatureBits()[arch::AsmCond2b] &&
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// COMPRESS-NEXT: (MRI.getRegClass(arch::RegsRegClassID).contains(MI.getOperand(0).getReg()))) {
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// COMPRESS-NEXT: // SmallInst2 $r
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def SmallInst3 : RVInst16<2, []>;
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def : CompressPat<(BigInst Regs:$r), (SmallInst3 Regs:$r), [AsmPred3]>;
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// COMPRESS: if ((STI.getFeatureBits()[arch::AsmCond3a] || STI.getFeatureBits()[arch::AsmCond3b]) &&
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// COMPRESS-NEXT: (MRI.getRegClass(arch::RegsRegClassID).contains(MI.getOperand(0).getReg()))) {
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// COMPRESS-NEXT: // SmallInst3 $r
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def SmallInst4 : RVInst16<2, []>;
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def : CompressPat<(BigInst Regs:$r), (SmallInst4 Regs:$r), [AsmPred1, AsmPred2]>;
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// COMPRESS: if (STI.getFeatureBits()[arch::AsmCond1] &&
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// COMPRESS-NEXT: STI.getFeatureBits()[arch::AsmCond2a] &&
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// COMPRESS-NEXT: STI.getFeatureBits()[arch::AsmCond2b] &&
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// COMPRESS-NEXT: (MRI.getRegClass(arch::RegsRegClassID).contains(MI.getOperand(0).getReg()))) {
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// COMPRESS-NEXT: // SmallInst4 $r
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def SmallInst5 : RVInst16<2, []>;
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def : CompressPat<(BigInst Regs:$r), (SmallInst5 Regs:$r), [AsmPred1, AsmPred3]>;
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// COMPRESS: if (STI.getFeatureBits()[arch::AsmCond1] &&
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// COMPRESS-NEXT: (STI.getFeatureBits()[arch::AsmCond3a] || STI.getFeatureBits()[arch::AsmCond3b]) &&
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// COMPRESS-NEXT: (MRI.getRegClass(arch::RegsRegClassID).contains(MI.getOperand(0).getReg()))) {
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// COMPRESS-NEXT: // SmallInst5 $r
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// COMPRESS-LABEL: static bool uncompressInst
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