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209 lines
11 KiB
TableGen
209 lines
11 KiB
TableGen
//==- AArch64SchedFalkor.td - Falkor Scheduling Definitions -*- tablegen -*-==//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines the machine model for Qualcomm Falkor to support
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// instruction scheduling and other instruction cost heuristics.
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//
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// Define the SchedMachineModel and provide basic properties for coarse grained
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// instruction cost model.
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def FalkorModel : SchedMachineModel {
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let IssueWidth = 4; // 4-wide issue for expanded uops.
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let MicroOpBufferSize = 128; // Out-of-order with temporary unified issue buffer.
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let LoopMicroOpBufferSize = 16;
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let LoadLatency = 3; // Optimistic load latency.
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let MispredictPenalty = 11; // Minimum branch misprediction penalty.
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let CompleteModel = 1;
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}
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//===----------------------------------------------------------------------===//
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// Define each kind of processor resource and number available on Falkor.
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let SchedModel = FalkorModel in {
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def FalkorUnitB : ProcResource<1>; // Branch
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def FalkorUnitLD : ProcResource<1>; // Load pipe
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def FalkorUnitSD : ProcResource<1>; // Store data
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def FalkorUnitST : ProcResource<1>; // Store pipe
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def FalkorUnitX : ProcResource<1>; // Complex arithmetic
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def FalkorUnitY : ProcResource<1>; // Simple arithmetic
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def FalkorUnitZ : ProcResource<1>; // Simple arithmetic
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def FalkorUnitVSD : ProcResource<1>; // Vector store data
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def FalkorUnitVX : ProcResource<1>; // Vector X-pipe
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def FalkorUnitVY : ProcResource<1>; // Vector Y-pipe
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// Define the resource groups.
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def FalkorUnitXYZ : ProcResGroup<[FalkorUnitX, FalkorUnitY, FalkorUnitZ]>;
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def FalkorUnitXYZB : ProcResGroup<[FalkorUnitX, FalkorUnitY, FalkorUnitZ,
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FalkorUnitB]>;
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def FalkorUnitZB : ProcResGroup<[FalkorUnitZ, FalkorUnitB]>;
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def FalkorUnitVXVY : ProcResGroup<[FalkorUnitVX, FalkorUnitVY]>;
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}
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//===----------------------------------------------------------------------===//
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// Map the target-defined scheduler read/write resources and latency for
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// Falkor.
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let SchedModel = FalkorModel in {
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def : WriteRes<WriteImm, [FalkorUnitXYZ]> { let Latency = 1; }
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def : WriteRes<WriteI, [FalkorUnitXYZ]> { let Latency = 1; }
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def : WriteRes<WriteISReg, [FalkorUnitVXVY, FalkorUnitVXVY]>
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{ let Latency = 1; let NumMicroOps = 2; }
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def : WriteRes<WriteIEReg, [FalkorUnitXYZ, FalkorUnitXYZ]>
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{ let Latency = 2; let NumMicroOps = 2; }
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def : WriteRes<WriteExtr, [FalkorUnitXYZ, FalkorUnitXYZ]>
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{ let Latency = 2; let NumMicroOps = 2; }
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def : WriteRes<WriteIS, [FalkorUnitXYZ]> { let Latency = 1; }
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def : WriteRes<WriteID32, [FalkorUnitX, FalkorUnitZ]>
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{ let Latency = 8; let NumMicroOps = 1; } // Fragent -1
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def : WriteRes<WriteID64, [FalkorUnitX, FalkorUnitZ]>
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{ let Latency = 8; let NumMicroOps = 1; } // Fragent -1
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def : WriteRes<WriteIM32, [FalkorUnitX]> { let Latency = 4; }
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def : WriteRes<WriteIM64, [FalkorUnitX]> { let Latency = 4; }
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def : WriteRes<WriteBr, [FalkorUnitB]> { let Latency = 1; }
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def : WriteRes<WriteBrReg, [FalkorUnitB]> { let Latency = 1; }
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def : WriteRes<WriteLD, [FalkorUnitLD]> { let Latency = 3; }
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def : WriteRes<WriteST, [FalkorUnitLD, FalkorUnitST, FalkorUnitSD]>
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{ let Latency = 3; let NumMicroOps = 3; }
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def : WriteRes<WriteSTP, [FalkorUnitST, FalkorUnitSD]>
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{ let Latency = 3; let NumMicroOps = 2; }
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def : WriteRes<WriteAdr, [FalkorUnitXYZ]> { let Latency = 5; }
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def : WriteRes<WriteLDIdx, [FalkorUnitLD]> { let Latency = 5; }
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def : WriteRes<WriteSTIdx, [FalkorUnitLD, FalkorUnitST, FalkorUnitSD]>
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{ let Latency = 4; let NumMicroOps = 3; }
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def : WriteRes<WriteF, [FalkorUnitVXVY, FalkorUnitVXVY]>
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{ let Latency = 3; let NumMicroOps = 2; }
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def : WriteRes<WriteFCmp, [FalkorUnitVXVY]> { let Latency = 2; }
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def : WriteRes<WriteFCvt, [FalkorUnitVXVY]> { let Latency = 4; }
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def : WriteRes<WriteFCopy, [FalkorUnitVXVY]> { let Latency = 4; }
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def : WriteRes<WriteFImm, [FalkorUnitVXVY]> { let Latency = 4; }
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def : WriteRes<WriteFMul, [FalkorUnitVXVY, FalkorUnitVXVY]>
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{ let Latency = 6; let NumMicroOps = 2; }
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def : WriteRes<WriteFDiv, [FalkorUnitVXVY, FalkorUnitVXVY]>
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{ let Latency = 12; let NumMicroOps = 2; } // Fragent -1 / NoRSV +1
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def : WriteRes<WriteV, [FalkorUnitVXVY]> { let Latency = 6; }
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def : WriteRes<WriteVLD, [FalkorUnitLD]> { let Latency = 3; }
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def : WriteRes<WriteVST, [FalkorUnitST]> { let Latency = 4; }
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def : WriteRes<WriteSys, []> { let Latency = 1; }
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def : WriteRes<WriteBarrier, []> { let Latency = 1; }
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def : WriteRes<WriteHint, []> { let Latency = 1; }
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def : WriteRes<WriteLDHi, []> { let Latency = 3; }
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def : WriteRes<WriteAtomic, []> { let Unsupported = 1; }
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// No forwarding logic is modelled yet.
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def : ReadAdvance<ReadI, 0>;
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def : ReadAdvance<ReadISReg, 0>;
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def : ReadAdvance<ReadIEReg, 0>;
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def : ReadAdvance<ReadIM, 0>;
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def : ReadAdvance<ReadIMA, 0>;
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def : ReadAdvance<ReadID, 0>;
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def : ReadAdvance<ReadExtrHi, 0>;
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def : ReadAdvance<ReadAdrBase, 0>;
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def : ReadAdvance<ReadVLD, 0>;
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//===----------------------------------------------------------------------===//
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// Specialize the coarse model by associating instruction groups with the
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// subtarget-defined types. As the modeled is refined, this will override most
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// of the above SchedWriteRes and SchedAlias mappings.
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// -----------------------------------------------------------------------------
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// Miscellaneous
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// -----------------------------------------------------------------------------
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def : InstRW<[WriteI], (instrs COPY)>;
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// -----------------------------------------------------------------------------
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// Vector Loads
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// -----------------------------------------------------------------------------
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def : InstRW<[WriteVLD], (instregex "LD1i(8|16|32|64)$")>;
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def : InstRW<[WriteVLD], (instregex "LD1Rv(8b|4h|2s|1d|16b|8h|4s|2d)$")>;
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def : InstRW<[WriteVLD], (instregex "LD1Onev(8b|4h|2s|1d|16b|8h|4s|2d)$")>;
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def : InstRW<[WriteVLD], (instregex "LD1Twov(8b|4h|2s|1d|16b|8h|4s|2d)$")>;
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def : InstRW<[WriteVLD], (instregex "LD1Threev(8b|4h|2s|1d|16b|8h|4s|2d)$")>;
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def : InstRW<[WriteVLD], (instregex "LD1Fourv(8b|4h|2s|1d|16b|8h|4s|2d)$")>;
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def : InstRW<[WriteVLD, WriteAdr], (instregex "LD1i(8|16|32|64)_POST$")>;
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def : InstRW<[WriteVLD, WriteAdr], (instregex "LD1Rv(8b|4h|2s|1d|16b|8h|4s|2d)_POST$")>;
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def : InstRW<[WriteVLD, WriteAdr], (instregex "LD1Onev(8b|4h|2s|1d|16b|8h|4s|2d)_POST$")>;
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def : InstRW<[WriteVLD, WriteAdr], (instregex "LD1Twov(8b|4h|2s|1d|16b|8h|4s|2d)_POST$")>;
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def : InstRW<[WriteVLD, WriteAdr], (instregex "LD1Threev(8b|4h|2s|1d|16b|8h|4s|2d)_POST$")>;
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def : InstRW<[WriteVLD, WriteAdr], (instregex "LD1Fourv(8b|4h|2s|1d|16b|8h|4s|2d)_POST$")>;
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def : InstRW<[WriteVLD], (instregex "LD2i(8|16|32|64)$")>;
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def : InstRW<[WriteVLD], (instregex "LD2Rv(8b|4h|2s|1d|16b|8h|4s|2d)$")>;
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def : InstRW<[WriteVLD], (instregex "LD2Twov(8b|4h|2s)$")>;
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def : InstRW<[WriteVLD], (instregex "LD2Twov(16b|8h|4s|2d)$")>;
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def : InstRW<[WriteVLD, WriteAdr], (instregex "LD2i(8|16|32|64)(_POST)?$")>;
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def : InstRW<[WriteVLD, WriteAdr], (instregex "LD2Rv(8b|4h|2s|1d|16b|8h|4s|2d)(_POST)?$")>;
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def : InstRW<[WriteVLD, WriteAdr], (instregex "LD2Twov(8b|4h|2s)(_POST)?$")>;
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def : InstRW<[WriteVLD, WriteAdr], (instregex "LD2Twov(16b|8h|4s|2d)(_POST)?$")>;
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def : InstRW<[WriteVLD], (instregex "LD3i(8|16|32|64)$")>;
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def : InstRW<[WriteVLD], (instregex "LD3Rv(8b|4h|2s|1d|16b|8h|4s|2d)$")>;
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def : InstRW<[WriteVLD], (instregex "LD3Threev(8b|4h|2s|1d|16b|8h|4s)$")>;
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def : InstRW<[WriteVLD], (instregex "LD3Threev(2d)$")>;
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def : InstRW<[WriteVLD, WriteAdr], (instregex "LD3i(8|16|32|64)_POST$")>;
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def : InstRW<[WriteVLD, WriteAdr], (instregex "LD3Rv(8b|4h|2s|1d|16b|8h|4s|2d)_POST$")>;
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def : InstRW<[WriteVLD, WriteAdr], (instregex "LD3Threev(8b|4h|2s|1d|16b|8h|4s)_POST$")>;
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def : InstRW<[WriteVLD, WriteAdr], (instregex "LD3Threev(2d)_POST$")>;
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def : InstRW<[WriteVLD], (instregex "LD4i(8|16|32|64)$")>;
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def : InstRW<[WriteVLD], (instregex "LD4Rv(8b|4h|2s|1d|16b|8h|4s|2d)$")>;
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def : InstRW<[WriteVLD], (instregex "LD4Fourv(8b|4h|2s|1d|16b|8h|4s)$")>;
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def : InstRW<[WriteVLD], (instregex "LD4Fourv(2d)$")>;
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def : InstRW<[WriteVLD, WriteAdr], (instregex "LD4i(8|16|32|64)_POST$")>;
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def : InstRW<[WriteVLD, WriteAdr], (instregex "LD4Rv(8b|4h|2s|1d|16b|8h|4s|2d)_POST$")>;
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def : InstRW<[WriteVLD, WriteAdr], (instregex "LD4Fourv(8b|4h|2s|1d|16b|8h|4s)_POST$")>;
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def : InstRW<[WriteVLD, WriteAdr], (instregex "LD4Fourv(2d)_POST$")>;
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// -----------------------------------------------------------------------------
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// Vector Stores
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// -----------------------------------------------------------------------------
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def : InstRW<[WriteVST], (instregex "ST1i(8|16|32|64)$")>;
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def : InstRW<[WriteVST], (instregex "ST1Onev(8b|4h|2s|1d|16b|8h|4s|2d)$")>;
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def : InstRW<[WriteVST], (instregex "ST1Twov(8b|4h|2s|1d|16b|8h|4s|2d)$")>;
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def : InstRW<[WriteVST], (instregex "ST1Threev(8b|4h|2s|1d|16b|8h|4s|2d)$")>;
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def : InstRW<[WriteVST], (instregex "ST1Fourv(8b|4h|2s|1d|16b|8h|4s|2d)$")>;
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def : InstRW<[WriteVST, WriteAdr], (instregex "ST1i(8|16|32|64)_POST$")>;
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def : InstRW<[WriteVST, WriteAdr], (instregex "ST1Onev(8b|4h|2s|1d|16b|8h|4s|2d)_POST$")>;
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def : InstRW<[WriteVST, WriteAdr], (instregex "ST1Twov(8b|4h|2s|1d|16b|8h|4s|2d)_POST$")>;
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def : InstRW<[WriteVST, WriteAdr], (instregex "ST1Threev(8b|4h|2s|1d|16b|8h|4s|2d)_POST$")>;
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def : InstRW<[WriteVST, WriteAdr], (instregex "ST1Fourv(8b|4h|2s|1d|16b|8h|4s|2d)_POST$")>;
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def : InstRW<[WriteVST], (instregex "ST2i(8|16|32|64)$")>;
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def : InstRW<[WriteVST], (instregex "ST2Twov(8b|4h|2s)$")>;
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def : InstRW<[WriteVST], (instregex "ST2Twov(16b|8h|4s|2d)$")>;
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def : InstRW<[WriteVST, WriteAdr], (instregex "ST2i(8|16|32|64)_POST$")>;
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def : InstRW<[WriteVST, WriteAdr], (instregex "ST2Twov(8b|4h|2s)_POST$")>;
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def : InstRW<[WriteVST, WriteAdr], (instregex "ST2Twov(16b|8h|4s|2d)_POST$")>;
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def : InstRW<[WriteVST], (instregex "ST3i(8|16|32|64)$")>;
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def : InstRW<[WriteVST], (instregex "ST3Threev(8b|4h|2s|1d|16b|8h|4s)$")>;
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def : InstRW<[WriteVST], (instregex "ST3Threev(2d)$")>;
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def : InstRW<[WriteVST, WriteAdr], (instregex "ST3i(8|16|32|64)_POST$")>;
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def : InstRW<[WriteVST, WriteAdr], (instregex "ST3Threev(8b|4h|2s|1d|16b|8h|4s)_POST$")>;
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def : InstRW<[WriteVST, WriteAdr], (instregex "ST3Threev(2d)_POST$")>;
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def : InstRW<[WriteVST], (instregex "ST4i(8|16|32|64)$")>;
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def : InstRW<[WriteVST], (instregex "ST4Fourv(8b|4h|2s|1d|16b|8h|4s)$")>;
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def : InstRW<[WriteVST], (instregex "ST4Fourv(2d)$")>;
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def : InstRW<[WriteVST, WriteAdr], (instregex "ST4i(8|16|32|64)_POST$")>;
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def : InstRW<[WriteVST, WriteAdr], (instregex "ST4Fourv(8b|4h|2s|1d|16b|8h|4s)_POST$")>;
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def : InstRW<[WriteVST, WriteAdr], (instregex "ST4Fourv(2d)_POST$")>;
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}
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