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llvm-mirror/lib/Target/X86/X86LegalizerInfo.h
Igor Breger 52c4471b99 [GlobalISel][X86] G_LOAD/G_STORE vec256/512 support
Summary: mark G_LOAD/G_STORE vec256/512 legal for AVX/AVX512. Implement instruction selection.

Reviewers: zvi, guyblank

Reviewed By: zvi

Subscribers: rovka, llvm-commits, kristof.beyls

Differential Revision: https://reviews.llvm.org/D33268

llvm-svn: 303617
2017-05-23 08:23:51 +00:00

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//===- X86LegalizerInfo.h ------------------------------------------*- C++
//-*-==//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
/// \file
/// This file declares the targeting of the Machinelegalizer class for X86.
/// \todo This should be generated by TableGen.
//===----------------------------------------------------------------------===//
#ifndef LLVM_LIB_TARGET_X86_X86MACHINELEGALIZER_H
#define LLVM_LIB_TARGET_X86_X86MACHINELEGALIZER_H
#include "llvm/CodeGen/GlobalISel/LegalizerInfo.h"
namespace llvm {
class X86Subtarget;
class X86TargetMachine;
/// This class provides the information for the target register banks.
class X86LegalizerInfo : public LegalizerInfo {
private:
/// Keep a reference to the X86Subtarget around so that we can
/// make the right decision when generating code for different targets.
const X86Subtarget &Subtarget;
const X86TargetMachine &TM;
public:
X86LegalizerInfo(const X86Subtarget &STI, const X86TargetMachine &TM);
private:
void setLegalizerInfo32bit();
void setLegalizerInfo64bit();
void setLegalizerInfoSSE1();
void setLegalizerInfoSSE2();
void setLegalizerInfoSSE41();
void setLegalizerInfoAVX();
void setLegalizerInfoAVX2();
void setLegalizerInfoAVX512();
void setLegalizerInfoAVX512DQ();
void setLegalizerInfoAVX512BW();
};
} // namespace llvm
#endif