mirror of
https://github.com/RPCS3/llvm-mirror.git
synced 2024-10-20 03:23:01 +02:00
e5be0665b2
This is a tablegen backend to generate documentation for the opcodes that exist for each target. For each opcode, it lists the assembly string, the names and types of all operands, and the flags and predicates that apply to the opcode. Differential revision: https://reviews.llvm.org/D31025 llvm-svn: 318155
48 lines
1.1 KiB
CMake
48 lines
1.1 KiB
CMake
set(LLVM_LINK_COMPONENTS Support)
|
|
|
|
add_tablegen(llvm-tblgen LLVM
|
|
AsmMatcherEmitter.cpp
|
|
AsmWriterEmitter.cpp
|
|
AsmWriterInst.cpp
|
|
Attributes.cpp
|
|
CallingConvEmitter.cpp
|
|
CodeEmitterGen.cpp
|
|
CodeGenDAGPatterns.cpp
|
|
CodeGenHwModes.cpp
|
|
CodeGenInstruction.cpp
|
|
CodeGenMapTable.cpp
|
|
CodeGenRegisters.cpp
|
|
CodeGenSchedule.cpp
|
|
CodeGenTarget.cpp
|
|
DAGISelEmitter.cpp
|
|
DAGISelMatcherEmitter.cpp
|
|
DAGISelMatcherGen.cpp
|
|
DAGISelMatcherOpt.cpp
|
|
DAGISelMatcher.cpp
|
|
DFAPacketizerEmitter.cpp
|
|
DisassemblerEmitter.cpp
|
|
FastISelEmitter.cpp
|
|
FixedLenDecoderEmitter.cpp
|
|
GlobalISelEmitter.cpp
|
|
InfoByHwMode.cpp
|
|
InstrInfoEmitter.cpp
|
|
InstrDocsEmitter.cpp
|
|
IntrinsicEmitter.cpp
|
|
OptParserEmitter.cpp
|
|
PseudoLoweringEmitter.cpp
|
|
RegisterBankEmitter.cpp
|
|
RegisterInfoEmitter.cpp
|
|
SearchableTableEmitter.cpp
|
|
SubtargetEmitter.cpp
|
|
SubtargetFeatureInfo.cpp
|
|
TableGen.cpp
|
|
Types.cpp
|
|
X86DisassemblerTables.cpp
|
|
X86EVEX2VEXTablesEmitter.cpp
|
|
X86FoldTablesEmitter.cpp
|
|
X86ModRMFilters.cpp
|
|
X86RecognizableInstr.cpp
|
|
CTagsEmitter.cpp
|
|
)
|
|
set_target_properties(llvm-tblgen PROPERTIES FOLDER "Tablegenning")
|