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AArch64
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Revert "[AArch64] Fix optimizeCondBranch logic."
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2016-04-23 19:30:52 +00:00 |
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AMDGPU
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AMDGPU: sext_inreg (srl x, K), vt -> bfe x, K, vt.Size
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2016-04-22 22:59:16 +00:00 |
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ARM
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Fix llvm/test/CodeGen/ARM/Windows/dbzchk.ll not to check mixed output, take #2.
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2016-04-22 22:51:48 +00:00 |
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BPF
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CPP
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Generic
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Introduce llvm.load.relative intrinsic.
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2016-04-22 21:18:02 +00:00 |
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Hexagon
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[Hexagon] Properly close live range in HexagonBlockRanges ---add testcase
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2016-04-22 17:30:13 +00:00 |
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Inputs
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[PR27284] Reverse the ownership between DICompileUnit and DISubprogram.
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2016-04-15 15:57:41 +00:00 |
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Lanai
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[lanai] Add subword scheduling itineraries.
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2016-04-20 18:28:55 +00:00 |
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Mips
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[mips] Fix select patterns for MIPS64
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2016-04-22 13:19:22 +00:00 |
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MIR
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[PR27284] Reverse the ownership between DICompileUnit and DISubprogram.
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2016-04-15 15:57:41 +00:00 |
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MSP430
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NVPTX
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[PR27284] Reverse the ownership between DICompileUnit and DISubprogram.
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2016-04-15 15:57:41 +00:00 |
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PowerPC
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use FileCheck; add test for disguised fabs
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2016-04-21 20:58:58 +00:00 |
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SPARC
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SystemZ
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[SystemZ] Add support for llvm.thread.pointer intrinsic.
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2016-04-20 01:03:48 +00:00 |
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Thumb
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[PR27284] Reverse the ownership between DICompileUnit and DISubprogram.
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2016-04-15 15:57:41 +00:00 |
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Thumb2
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WebAssembly
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[WebAssembly] Limit alignment hints to natural alignment.
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2016-04-21 23:59:48 +00:00 |
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WinEH
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[PR27284] Reverse the ownership between DICompileUnit and DISubprogram.
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2016-04-15 15:57:41 +00:00 |
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X86
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[X86] Fix patterns that turn cmove/cmovne+ctlz/cttz into lzcnt/tzcnt instructions. Only one of the conditions should be valid for each pattern, not both. Update tests accordingly.
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2016-04-24 02:01:22 +00:00 |
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XCore
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[PR27284] Reverse the ownership between DICompileUnit and DISubprogram.
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2016-04-15 15:57:41 +00:00 |
