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65266a8e22
As discussed in D11760, this patch moves the (V)PSRA(WD) arithmetic shift-by-constant folding to InstCombine to match the logical shift implementations. Differential Revision: http://reviews.llvm.org/D11886 llvm-svn: 244495
120 lines
3.6 KiB
LLVM
120 lines
3.6 KiB
LLVM
; RUN: llc < %s -march=x86-64 -mcpu=core-avx2 | FileCheck %s
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; Verify that the backend correctly combines AVX2 builtin intrinsics.
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define <32 x i8> @test_x86_avx2_pblendvb(<32 x i8> %a0, <32 x i8> %a1) {
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%res = call <32 x i8> @llvm.x86.avx2.pblendvb(<32 x i8> %a0, <32 x i8> %a0, <32 x i8> %a1)
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ret <32 x i8> %res
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}
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; CHECK-LABEL: test_x86_avx2_pblendvb
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; CHECK-NOT: vpblendvb
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; CHECK: ret
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define <16 x i16> @test_x86_avx2_pblendw(<16 x i16> %a0) {
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%res = call <16 x i16> @llvm.x86.avx2.pblendw(<16 x i16> %a0, <16 x i16> %a0, i32 7)
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ret <16 x i16> %res
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}
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; CHECK-LABEL: test_x86_avx2_pblendw
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; CHECK-NOT: vpblendw
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; CHECK: ret
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define <4 x i32> @test_x86_avx2_pblendd_128(<4 x i32> %a0) {
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%res = call <4 x i32> @llvm.x86.avx2.pblendd.128(<4 x i32> %a0, <4 x i32> %a0, i32 7)
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ret <4 x i32> %res
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}
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; CHECK-LABEL: test_x86_avx2_pblendd_128
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; CHECK-NOT: vpblendd
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; CHECK: ret
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define <8 x i32> @test_x86_avx2_pblendd_256(<8 x i32> %a0) {
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%res = call <8 x i32> @llvm.x86.avx2.pblendd.256(<8 x i32> %a0, <8 x i32> %a0, i32 7)
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ret <8 x i32> %res
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}
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; CHECK-LABEL: test_x86_avx2_pblendd_256
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; CHECK-NOT: vpblendd
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; CHECK: ret
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define <32 x i8> @test2_x86_avx2_pblendvb(<32 x i8> %a0, <32 x i8> %a1) {
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%res = call <32 x i8> @llvm.x86.avx2.pblendvb(<32 x i8> %a0, <32 x i8> %a1, <32 x i8> zeroinitializer)
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ret <32 x i8> %res
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}
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; CHECK-LABEL: test2_x86_avx2_pblendvb
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; CHECK-NOT: vpblendvb
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; CHECK: ret
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define <16 x i16> @test2_x86_avx2_pblendw(<16 x i16> %a0, <16 x i16> %a1) {
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%res = call <16 x i16> @llvm.x86.avx2.pblendw(<16 x i16> %a0, <16 x i16> %a1, i32 0)
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ret <16 x i16> %res
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}
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; CHECK-LABEL: test2_x86_avx2_pblendw
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; CHECK-NOT: vpblendw
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; CHECK: ret
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define <4 x i32> @test2_x86_avx2_pblendd_128(<4 x i32> %a0, <4 x i32> %a1) {
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%res = call <4 x i32> @llvm.x86.avx2.pblendd.128(<4 x i32> %a0, <4 x i32> %a1, i32 0)
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ret <4 x i32> %res
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}
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; CHECK-LABEL: test2_x86_avx2_pblendd_128
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; CHECK-NOT: vpblendd
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; CHECK: ret
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define <8 x i32> @test2_x86_avx2_pblendd_256(<8 x i32> %a0, <8 x i32> %a1) {
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%res = call <8 x i32> @llvm.x86.avx2.pblendd.256(<8 x i32> %a0, <8 x i32> %a1, i32 0)
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ret <8 x i32> %res
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}
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; CHECK-LABEL: test2_x86_avx2_pblendd_256
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; CHECK-NOT: vpblendd
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; CHECK: ret
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define <32 x i8> @test3_x86_avx2_pblendvb(<32 x i8> %a0, <32 x i8> %a1) {
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%1 = bitcast <4 x i64> <i64 -1, i64 -1, i64 -1, i64 -1> to <32 x i8>
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%res = call <32 x i8> @llvm.x86.avx2.pblendvb(<32 x i8> %a0, <32 x i8> %a1, <32 x i8> %1)
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ret <32 x i8> %res
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}
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; CHECK-LABEL: test3_x86_avx2_pblendvb
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; CHECK-NOT: vpblendvb
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; CHECK: ret
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define <16 x i16> @test3_x86_avx2_pblendw(<16 x i16> %a0, <16 x i16> %a1) {
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%res = call <16 x i16> @llvm.x86.avx2.pblendw(<16 x i16> %a0, <16 x i16> %a1, i32 -1)
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ret <16 x i16> %res
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}
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; CHECK-LABEL: test3_x86_avx2_pblendw
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; CHECK-NOT: vpblendw
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; CHECK: ret
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define <4 x i32> @test3_x86_avx2_pblendd_128(<4 x i32> %a0, <4 x i32> %a1) {
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%res = call <4 x i32> @llvm.x86.avx2.pblendd.128(<4 x i32> %a0, <4 x i32> %a1, i32 -1)
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ret <4 x i32> %res
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}
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; CHECK-LABEL: test3_x86_avx2_pblendd_128
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; CHECK-NOT: vpblendd
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; CHECK: ret
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define <8 x i32> @test3_x86_avx2_pblendd_256(<8 x i32> %a0, <8 x i32> %a1) {
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%res = call <8 x i32> @llvm.x86.avx2.pblendd.256(<8 x i32> %a0, <8 x i32> %a1, i32 -1)
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ret <8 x i32> %res
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}
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; CHECK-LABEL: test3_x86_avx2_pblendd_256
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; CHECK-NOT: vpblendd
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; CHECK: ret
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declare <32 x i8> @llvm.x86.avx2.pblendvb(<32 x i8>, <32 x i8>, <32 x i8>)
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declare <16 x i16> @llvm.x86.avx2.pblendw(<16 x i16>, <16 x i16>, i32)
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declare <4 x i32> @llvm.x86.avx2.pblendd.128(<4 x i32>, <4 x i32>, i32)
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declare <8 x i32> @llvm.x86.avx2.pblendd.256(<8 x i32>, <8 x i32>, i32)
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