Hrvoje Varga 52c95ef5b8 [mips][micromips] Implement LD, LLD, LWU, SD, DSRL, DSRL32 and DSRLV instructions ...

Differential Revision: http://reviews.llvm.org/D16625

llvm-svn: 273850

2016-06-27 08:23:28 +00:00

..

invalid-mips3-wrong-error.s

[mips][micromips] Implement LD, LLD, LWU, SD, DSRL, DSRL32 and DSRLV instructions

2016-06-27 08:23:28 +00:00

invalid-mips3.s

[mips][micromips] Implement LD, LLD, LWU, SD, DSRL, DSRL32 and DSRLV instructions

2016-06-27 08:23:28 +00:00

invalid-mips4-wrong-error.s

[mips][micromips] Implement LD, LLD, LWU, SD, DSRL, DSRL32 and DSRLV instructions

2016-06-27 08:23:28 +00:00

invalid-mips4.s

[mips][micromips] Implement LD, LLD, LWU, SD, DSRL, DSRL32 and DSRLV instructions

2016-06-27 08:23:28 +00:00

invalid-mips5-wrong-error.s

[mips] Improve the error messages given by MipsAsmParser.

2014-09-16 15:00:52 +00:00

invalid-mips5.s

[mips][mips64r6] bc1[tf] are not available on MIPS32r6/MIPS64r6

2014-06-12 15:00:17 +00:00

invalid-mips32.s

[mips] SYNC $stype instruction was added in Mips32

2014-06-18 17:10:30 +00:00

invalid-mips32r2-xfail.s

[mips] Marked up instructions added in MIPS32r2 and tested that IAS for -mcpu=mips(2|32) does not accept them

2014-05-13 11:45:36 +00:00

invalid-mips32r2.s

[mips] Marked the DI/EI instruction aliases as MIPS32r2

2014-10-16 15:23:52 +00:00

valid.s

[mips] Weaken asm predicate for memory offsets

2016-05-27 13:56:36 +00:00