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llvm-mirror/utils/TableGen
Daniel Sanders 3d06a1da65 [tablegen] Improve performance of -gen-register-info by replacing barely-necessary std::map with a sorted vector
Summary:
This particular map is hardly ever queried and has a phased usage pattern (insert,
iterate, query, insert, iterate) so it's a good candidate for a sorted vector and
std::lower_bound.

This significantly reduces the run time of runTargetDesc() in some circumstances.
One llvm-tblgen invocation in my build improves the time spent in runTargetDesc()
from 9.86s down to 0.80s (~92%) without changing the output. The same invocation
also has 2GB less allocation churn.

Reviewers: bogner, rtereshin, aditya_nandakumar, volkan

Reviewed By: rtereshin

Subscribers: mgrang, dexonsmith, llvm-commits

Differential Revision: https://reviews.llvm.org/D50272

llvm-svn: 339208
2018-08-08 00:19:59 +00:00
..
AsmMatcherEmitter.cpp [Tablegen] Optimize isSubsetOf() in AsmMatcherEmitter.cpp. NFC 2018-07-13 16:36:14 +00:00
AsmWriterEmitter.cpp [TableGen] Prevent double flattening of InstAlias asm strings in the asm matcher emitter. 2018-06-18 01:28:01 +00:00
AsmWriterInst.cpp
AsmWriterInst.h
Attributes.cpp
CallingConvEmitter.cpp
CMakeLists.txt [RFC][Patch 1/3] Add a new class of predicates for variant scheduling classes. 2018-05-25 15:55:37 +00:00
CodeEmitterGen.cpp
CodeGenDAGPatterns.cpp Fix build bot after r338521 2018-08-01 12:07:32 +00:00
CodeGenDAGPatterns.h [TableGen] std::move vectors into TreePatternNode. 2018-07-15 06:52:49 +00:00
CodeGenHwModes.cpp
CodeGenHwModes.h
CodeGenInstruction.cpp [cfi-verify] Support AArch64. 2018-07-13 15:19:33 +00:00
CodeGenInstruction.h [cfi-verify] Support AArch64. 2018-07-13 15:19:33 +00:00
CodeGenIntrinsics.h
CodeGenMapTable.cpp
CodeGenRegisters.cpp [X86] Add phony registers for high halves of regs with low halves 2018-07-02 19:05:09 +00:00
CodeGenRegisters.h [TableGen] Fix leaking synthesized registers. 2018-05-29 16:55:06 +00:00
CodeGenSchedule.cpp Revert r338365: [X86] Improved sched models for X86 BT*rr instructions. 2018-07-31 13:00:51 +00:00
CodeGenSchedule.h Revert r338365: [X86] Improved sched models for X86 BT*rr instructions. 2018-07-31 13:00:51 +00:00
CodeGenTarget.cpp [GlobalISel][Tablegen] Assign small opcodes to pseudos 2018-05-23 22:10:21 +00:00
CodeGenTarget.h [GlobalISel][Tablegen] Assign small opcodes to pseudos 2018-05-23 22:10:21 +00:00
CTagsEmitter.cpp [TableGen] Change std::sort to llvm::sort in response to r327219 2018-04-06 20:18:05 +00:00
DAGISelEmitter.cpp [TableGen] Support multi-alternative pattern fragments 2018-07-13 13:18:00 +00:00
DAGISelMatcher.cpp
DAGISelMatcher.h
DAGISelMatcherEmitter.cpp
DAGISelMatcherGen.cpp [TableGen] Support multi-alternative pattern fragments 2018-07-13 13:18:00 +00:00
DAGISelMatcherOpt.cpp Rename DEBUG macro to LLVM_DEBUG. 2018-05-14 12:53:11 +00:00
DFAPacketizerEmitter.cpp Rename DEBUG macro to LLVM_DEBUG. 2018-05-14 12:53:11 +00:00
DisassemblerEmitter.cpp [WebAssembly] Initial Disassembler. 2018-05-10 22:16:44 +00:00
FastISelEmitter.cpp Revert r334764, as it breaks some bots 2018-06-14 20:32:58 +00:00
FixedLenDecoderEmitter.cpp [windows] Don't inline fieldFromInstruction on Windows 2018-07-25 17:33:20 +00:00
GlobalISelEmitter.cpp [NFC] Prefer (void) to LLVM_ATTRIBUTE_UNUSED for unused var in GlobalISElemitter.cpp. 2018-06-26 07:05:08 +00:00
InfoByHwMode.cpp [TableGen] Change std::sort to llvm::sort in response to r327219 2018-04-06 20:18:05 +00:00
InfoByHwMode.h
InstrDocsEmitter.cpp [cfi-verify] Support AArch64. 2018-07-13 15:19:33 +00:00
InstrInfoEmitter.cpp [cfi-verify] Support AArch64. 2018-07-13 15:19:33 +00:00
IntrinsicEmitter.cpp [Power9] Add __float128 builtins for Round To Odd 2018-07-09 18:50:06 +00:00
LLVMBuild.txt
OptParserEmitter.cpp
PredicateExpander.cpp [Tablegen][PredicateExpander] Add the ability to define checks for invalid registers. 2018-07-18 11:03:22 +00:00
PredicateExpander.h [Tablegen][PredicateExpander] Add the ability to define checks for invalid registers. 2018-07-18 11:03:22 +00:00
PseudoLoweringEmitter.cpp Rename DEBUG macro to LLVM_DEBUG. 2018-05-14 12:53:11 +00:00
RegisterBankEmitter.cpp Rename DEBUG macro to LLVM_DEBUG. 2018-05-14 12:53:11 +00:00
RegisterInfoEmitter.cpp [tablegen] Improve performance of -gen-register-info by replacing barely-necessary std::map with a sorted vector 2018-08-08 00:19:59 +00:00
RISCVCompressInstEmitter.cpp Rename DEBUG macro to LLVM_DEBUG. 2018-05-14 12:53:11 +00:00
SDNodeProperties.cpp
SDNodeProperties.h
SearchableTableEmitter.cpp TableGen/SearchableTables: Support more generic enums and tables 2018-06-21 13:36:22 +00:00
SequenceToOffsetTable.h
SubtargetEmitter.cpp [TableGen] Emit a fatal error on inconsistencies in resource units vs cycles. 2018-06-13 09:41:49 +00:00
SubtargetFeatureInfo.cpp IWYU for llvm-config.h in llvm, additions. 2018-04-30 14:59:11 +00:00
SubtargetFeatureInfo.h Remove \brief commands from doxygen comments. 2018-05-01 15:54:18 +00:00
TableGen.cpp [TableGen] Add a general-purpose JSON backend. 2018-07-11 08:40:19 +00:00
TableGenBackends.h [IR] Split Intrinsics.inc into enums and implementations 2018-06-23 02:02:38 +00:00
tdtags
Types.cpp
Types.h
WebAssemblyDisassemblerEmitter.cpp [WebAssembly] Initial Disassembler. 2018-05-10 22:16:44 +00:00
WebAssemblyDisassemblerEmitter.h [WebAssembly] Initial Disassembler. 2018-05-10 22:16:44 +00:00
X86DisassemblerShared.h
X86DisassemblerTables.cpp [X86] Remove DATA32_PREFIX. Hack the printing for DATA16_PREFIX to print 'data32' in 16-bit mode. Hack the asm parser to convert 'data32' to 'data16' in 16-bit mode. 2018-04-22 00:52:02 +00:00
X86DisassemblerTables.h
X86EVEX2VEXTablesEmitter.cpp [X86] Add the ability to force an EVEX2VEX mapping table entry from the .td files. Remove remaining manual table entries from the tablegen emitter. 2018-06-19 04:24:44 +00:00
X86FoldTablesEmitter.cpp [X86] More additions to the load folding tables based on the autogenerated tables. 2018-06-16 23:25:50 +00:00
X86ModRMFilters.cpp
X86ModRMFilters.h
X86RecognizableInstr.cpp [X86] Add a new VEX_WPrefix encoding to tag EVEX instruction that have VEX.W==1, but can be converted to their VEX equivalent that uses VEX.W==0. 2018-06-19 04:24:42 +00:00
X86RecognizableInstr.h [X86] Add a new VEX_WPrefix encoding to tag EVEX instruction that have VEX.W==1, but can be converted to their VEX equivalent that uses VEX.W==0. 2018-06-19 04:24:42 +00:00