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7f4328cecf
There's more smarts in AArch64ISelLowering that we don't have yet, but this change incrementally improves some of the more common patterns. I think future iterations will want to use some combination of PostLegalizerCombiner and the selector to catch the other cases. Differential Revision: https://reviews.llvm.org/D82340
21 lines
711 B
LLVM
21 lines
711 B
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -O0 -mtriple=aarch64-unknown-unknown | FileCheck %s
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define <2 x i64> @z(i64* nocapture nonnull readonly %p) {
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; CHECK-LABEL: z:
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; CHECK: // %bb.0:
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; CHECK-NEXT: adrp x8, .LCPI0_0
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; CHECK-NEXT: ldr q0, [x8, :lo12:.LCPI0_0]
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; CHECK-NEXT: ldr x8, [x0]
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; CHECK-NEXT: ldr x9, [x0, #8]
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; CHECK-NEXT: mov v0.d[0], x8
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; CHECK-NEXT: mov v0.d[1], x9
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; CHECK-NEXT: ret
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%b = load i64, i64* %p
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%p2 = getelementptr i64, i64* %p, i64 1
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%bb = load i64, i64* %p2
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%r1 = insertelement <2 x i64> zeroinitializer, i64 %b, i32 0
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%r2 = insertelement <2 x i64> %r1, i64 %bb, i32 1
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ret <2 x i64> %r2
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}
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