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63a18b6d87
This is a union of these commits:
* R600/SI: Enable more tests for VI which need no changes
* R600/SI: Enable V_BCNT tests for VI
Differences:
- v_bcnt_..._e32 -> _e64
- s_load_dword* inline offset is in bytes instead of dwords
* R600/SI: Enable all tests for VI which use S_LOAD_DWORD
The inline offset is changed from dwords to bytes.
* R600/SI: Enable LDS tests for VI
Differences:
- the s_load_dword inline offset changed from dwords to bytes
- the tests checked very little on CI, so they have been fixed to check all
instructions that "SI" checked
* R600/SI: Enable lshr tests for VI
* R600/SI: Fix divrem64 tests
- "v_lshl_64" was missing "b" before "64"
- added VI-NOT checks
* R600/SI: Enable the SI.tid test for VI
* R600/SI: Enable the frem test for VI
Also, the frem_f64 checking is added for CI-VI.
* R600/SI: Add VI tests for rsq.clamped
llvm-svn: 228830
24 lines
1.0 KiB
LLVM
24 lines
1.0 KiB
LLVM
; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
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; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=VI -check-prefix=FUNC %s
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declare double @llvm.AMDGPU.rsq.clamped.f64(double) nounwind readnone
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; FUNC-LABEL: {{^}}rsq_clamped_f64:
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; SI: v_rsq_clamp_f64_e32
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; VI: v_rsq_f64_e32 [[RSQ:v\[[0-9]+:[0-9]+\]]], s[2:3]
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; TODO: this constant should be folded:
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; VI: s_mov_b32 s[[ALLBITS:[0-9+]]], -1
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; VI: s_mov_b32 s[[HIGH1:[0-9+]]], 0x7fefffff
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; VI: s_mov_b32 s[[LOW1:[0-9+]]], s[[ALLBITS]]
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; VI: v_min_f64 v[0:1], [[RSQ]], s{{\[}}[[LOW1]]:[[HIGH1]]]
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; VI: s_mov_b32 s[[HIGH2:[0-9+]]], 0xffefffff
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; VI: s_mov_b32 s[[LOW2:[0-9+]]], s[[ALLBITS]]
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; VI: v_max_f64 v[0:1], v[0:1], s{{\[}}[[LOW2]]:[[HIGH2]]]
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define void @rsq_clamped_f64(double addrspace(1)* %out, double %src) nounwind {
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%rsq_clamped = call double @llvm.AMDGPU.rsq.clamped.f64(double %src) nounwind readnone
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store double %rsq_clamped, double addrspace(1)* %out, align 8
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ret void
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}
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