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llvm-mirror/test/MC/Disassembler/AMDGPU/trap_vi.txt
Dmitry Preobrazhensky b8925d0036 [AMDGPU][MC] Added support of 256- and 512-bit tuples of ttmp registers
See bug 35561: https://bugs.llvm.org/show_bug.cgi?id=35561

This patch also affects implementation of SGPR and VGPR registers though changes are cosmetic.

Reviewers: artem.tamazov, arsenm

Differential Revision: https://reviews.llvm.org/D41437

llvm-svn: 321359
2017-12-22 15:18:06 +00:00

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# RUN: llvm-mc -arch=amdgcn -mcpu=tonga -disassemble -show-encoding < %s | FileCheck %s -check-prefix=VI
#===----------------------------------------------------------------------===#
# Trap Handler related - 32 bit registers
#===----------------------------------------------------------------------===#
# VI: s_add_u32 ttmp0, ttmp0, 4 ; encoding: [0x70,0x84,0x70,0x80]
0x70,0x84,0x70,0x80
# VI: s_add_u32 ttmp4, 8, ttmp4 ; encoding: [0x88,0x74,0x74,0x80]
0x88,0x74,0x74,0x80
# VI: s_add_u32 ttmp4, ttmp4, 0x100 ; encoding: [0x74,0xff,0x74,0x80,0x00,0x01,0x00,0x00]
0x74,0xff,0x74,0x80,0x00,0x01,0x00,0x00
# VI: s_add_u32 ttmp4, ttmp4, 4 ; encoding: [0x74,0x84,0x74,0x80]
0x74,0x84,0x74,0x80
# VI: s_add_u32 ttmp4, ttmp8, ttmp4 ; encoding: [0x78,0x74,0x74,0x80]
0x78,0x74,0x74,0x80
# VI: s_and_b32 ttmp10, ttmp8, 0x80 ; encoding: [0x78,0xff,0x7a,0x86,0x80,0x00,0x00,0x00]
0x78,0xff,0x7a,0x86,0x80,0x00,0x00,0x00
# VI: s_and_b32 ttmp9, tma_hi, 0xffff ; encoding: [0x6f,0xff,0x79,0x86,0xff,0xff,0x00,0x00]
0x6f,0xff,0x79,0x86,0xff,0xff,0x00,0x00
# VI: s_and_b32 ttmp9, ttmp9, 0x1ff ; encoding: [0x79,0xff,0x79,0x86,0xff,0x01,0x00,0x00]
0x79,0xff,0x79,0x86,0xff,0x01,0x00,0x00
# VI: s_and_b32 ttmp9, tma_lo, 0xffff0000 ; encoding: [0x6e,0xff,0x79,0x86,0x00,0x00,0xff,0xff]
0x6e,0xff,0x79,0x86,0x00,0x00,0xff,0xff
# VI: s_and_b32 ttmp9, ttmp9, ttmp8 ; encoding: [0x79,0x78,0x79,0x86]
0x79,0x78,0x79,0x86
# VI: s_and_b32 ttmp8, ttmp1, 0x1000000 ; encoding: [0x71,0xff,0x78,0x86,0x00,0x00,0x00,0x01]
0x71,0xff,0x78,0x86,0x00,0x00,0x00,0x01
# VI: s_cmp_eq_i32 ttmp8, 0 ; encoding: [0x78,0x80,0x00,0xbf]
0x78,0x80,0x00,0xbf
# VI: s_cmp_eq_i32 ttmp8, 0xfe ; encoding: [0x78,0xff,0x00,0xbf,0xfe,0x00,0x00,0x00]
0x78,0xff,0x00,0xbf,0xfe,0x00,0x00,0x00
# VI: s_lshr_b32 ttmp8, ttmp8, 12 ; encoding: [0x78,0x8c,0x78,0x8f]
0x78,0x8c,0x78,0x8f
# VI: v_mov_b32_e32 v1, ttmp8 ; encoding: [0x78,0x02,0x02,0x7e]
0x78,0x02,0x02,0x7e
# VI: s_mov_b32 m0, ttmp8 ; encoding: [0x78,0x00,0xfc,0xbe]
0x78,0x00,0xfc,0xbe
# VI: s_mov_b32 ttmp10, 0 ; encoding: [0x80,0x00,0xfa,0xbe]
0x80,0x00,0xfa,0xbe
# VI: s_mov_b32 ttmp11, 0x1024fac ; encoding: [0xff,0x00,0xfb,0xbe,0xac,0x4f,0x02,0x01]
0xff,0x00,0xfb,0xbe,0xac,0x4f,0x02,0x01
# VI: s_mov_b32 ttmp8, m0 ; encoding: [0x7c,0x00,0xf8,0xbe]
0x7c,0x00,0xf8,0xbe
# VI: s_mov_b32 ttmp8, tma_lo ; encoding: [0x6e,0x00,0xf8,0xbe]
0x6e,0x00,0xf8,0xbe
# VI: s_mul_i32 ttmp8, 0x324, ttmp8 ; encoding: [0xff,0x78,0x78,0x92,0x24,0x03,0x00,0x00]
0xff,0x78,0x78,0x92,0x24,0x03,0x00,0x00
# VI: s_or_b32 ttmp9, ttmp9, 0x280000 ; encoding: [0x79,0xff,0x79,0x87,0x00,0x00,0x28,0x00]
0x79,0xff,0x79,0x87,0x00,0x00,0x28,0x00
#===----------------------------------------------------------------------===#
# Trap Handler related - Pairs and quadruples of registers
#===----------------------------------------------------------------------===#
# VI: s_mov_b64 ttmp[4:5], exec ; encoding: [0x7e,0x01,0xf4,0xbe]
0x7e,0x01,0xf4,0xbe
# VI: s_mov_b64 ttmp[4:5], exec ; encoding: [0x7e,0x01,0xf4,0xbe]
0x7e,0x01,0xf4,0xbe
# VI: s_mov_b64 exec, ttmp[4:5] ; encoding: [0x74,0x01,0xfe,0xbe]
0x74,0x01,0xfe,0xbe
# VI: s_mov_b64 tba, ttmp[4:5] ; encoding: [0x74,0x01,0xec,0xbe]
0x74,0x01,0xec,0xbe
# VI: s_mov_b64 ttmp[4:5], tba ; encoding: [0x6c,0x01,0xf4,0xbe]
0x6c,0x01,0xf4,0xbe
# VI: s_mov_b64 tma, ttmp[4:5] ; encoding: [0x74,0x01,0xee,0xbe]
0x74,0x01,0xee,0xbe
# VI: s_mov_b64 ttmp[4:5], tma ; encoding: [0x6e,0x01,0xf4,0xbe]
0x6e,0x01,0xf4,0xbe
#===----------------------------------------------------------------------===#
# Trap Handler related - Some specific instructions
#===----------------------------------------------------------------------===#
# VI: s_setpc_b64 ttmp[2:3] ; encoding: [0x72,0x1d,0x80,0xbe]
0x72,0x1d,0x80,0xbe
# VI: v_readfirstlane_b32 ttmp8, v1 ; encoding: [0x01,0x05,0xf0,0x7e]
0x01,0x05,0xf0,0x7e
# VI: buffer_atomic_inc v1, off, ttmp[8:11], 56 glc ; encoding: [0x00,0x40,0x2c,0xe1,0x00,0x01,0x1e,0xb8]
0x00,0x40,0x2c,0xe1,0x00,0x01,0x1e,0xb8
#===----------------------------------------------------------------------===#
# Trap Handler related - 8-dword registers
#===----------------------------------------------------------------------===#
# VI: s_buffer_load_dwordx8 ttmp[0:7], s[0:3], s0 ; encoding: [0x00,0x1c,0x2c,0xc0,0x00,0x00,0x00,0x00]
0x00,0x1c,0x2c,0xc0,0x00,0x00,0x00,0x00
# VI: s_buffer_load_dwordx8 ttmp[4:11], s[0:3], s0 ; encoding: [0x00,0x1d,0x2c,0xc0,0x00,0x00,0x00,0x00]
0x00,0x1d,0x2c,0xc0,0x00,0x00,0x00,0x00
# VI: s_load_dwordx8 ttmp[0:7], s[0:1], s0 ; encoding: [0x00,0x1c,0x0c,0xc0,0x00,0x00,0x00,0x00]
0x00,0x1c,0x0c,0xc0,0x00,0x00,0x00,0x00
# VI: s_load_dwordx8 ttmp[4:11], s[0:1], s0 ; encoding: [0x00,0x1d,0x0c,0xc0,0x00,0x00,0x00,0x00]
0x00,0x1d,0x0c,0xc0,0x00,0x00,0x00,0x00