Craig Topper 929845dd01 [AVX-512] Add support for creating SIGN_EXTEND_VECTOR_INREG and ZERO_EXTEND_VECTOR_INREG for 512-bit vectors to support vpmovzxbq and vpmovsxbq. ... Summary: The one tricky thing about this is that the sign/zero_extend_inreg uses v64i8 as an input type which isn't legal without BWI support. Though the vpmovsxbq and vpmovzxbq instructions themselves don't require BWI. To support this we need to add custom lowering for ZERO_EXTEND_VECTOR_INREG with v64i8 input. This can mostly reuse the existing sign extend code with a couple checks for sign extend vs zero extend added. Reviewers: delena, RKSimon Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D25594 llvm-svn: 285053		2016-10-25 04:00:29 +00:00
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Analysis	Fix regression from my recent GlobalsAA fix.	2016-10-24 21:47:44 +00:00
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CodeGen	[AVX-512] Add support for creating SIGN_EXTEND_VECTOR_INREG and ZERO_EXTEND_VECTOR_INREG for 512-bit vectors to support vpmovzxbq and vpmovsxbq.	2016-10-25 04:00:29 +00:00
DebugInfo	[pdb] added support for dumping globals stream	2016-10-21 19:43:19 +00:00
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MC	[MC] Fix Various End Of Line Comment checkings	2016-10-24 14:35:29 +00:00
Object	nother additional error check for an invalid Mach-O file	2016-10-24 21:15:11 +00:00
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tools	[llvm-cov] Do not print out the filename of the object file	2016-10-25 00:08:33 +00:00
Transforms	[InstCombine] auto-generate checks	2016-10-25 00:44:02 +00:00
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