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https://github.com/RPCS3/llvm-mirror.git
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50e1810fbf
Previously, getWithOffset() would drop the offset if the base was null. Because of this, MachineMemOperand would return the wrong result from getAlign() in these cases. MachineMemOperand stores the alignment of the pointer without the offset. A bunch of MIR tests changed because we print the offset now. Split off from D77687. Differential Revision: https://reviews.llvm.org/D78049
220 lines
7.2 KiB
YAML
220 lines
7.2 KiB
YAML
# RUN: llc -mtriple arm-- -run-pass=legalizer %s -o - | FileCheck %s
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# RUN: llc -mtriple thumbv7-- -run-pass=legalizer %s -o - | FileCheck %s
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--- |
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define void @test_legal_loads_stores() { ret void }
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define void @test_load_from_stack() { ret void }
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define void @test_load_store_64_vfp() #0 { ret void }
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define void @test_load_store_64_novfp() #1 { ret void }
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define void @test_gep_s32() { ret void }
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define void @test_gep_s16() { ret void }
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attributes #0 = { "target-features"="+vfp2" }
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attributes #1 = { "target-features"="-vfp2sp" }
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...
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---
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name: test_legal_loads_stores
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# CHECK-LABEL: name: test_legal_loads_stores
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legalized: false
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# CHECK: legalized: true
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regBankSelected: false
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selected: false
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tracksRegLiveness: true
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registers:
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- { id: 0, class: _ }
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- { id: 1, class: _ }
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- { id: 2, class: _ }
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- { id: 3, class: _ }
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- { id: 4, class: _ }
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- { id: 5, class: _ }
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- { id: 6, class: _ }
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body: |
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bb.0:
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liveins: $r0
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; These are all legal, so we should find them unchanged in the output
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; CHECK-DAG: G_STORE {{%[0-9]+}}(s32), %0(p0)
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; CHECK-DAG: G_STORE {{%[0-9]+}}(s16), %0(p0)
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; CHECK-DAG: G_STORE {{%[0-9]+}}(s8), %0(p0)
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; CHECK-DAG: G_STORE {{%[0-9]+}}(s1), %0(p0)
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; CHECK-DAG: G_STORE {{%[0-9]+}}(p0), %0(p0)
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; CHECK-DAG: {{%[0-9]+}}:_(s32) = G_LOAD %0(p0)
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; CHECK-DAG: {{%[0-9]+}}:_(s16) = G_LOAD %0(p0)
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; CHECK-DAG: {{%[0-9]+}}:_(s8) = G_LOAD %0(p0)
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; CHECK-DAG: {{%[0-9]+}}:_(s1) = G_LOAD %0(p0)
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; CHECK-DAG: {{%[0-9]+}}:_(p0) = G_LOAD %0(p0)
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%0(p0) = COPY $r0
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%2(s32) = G_LOAD %0(p0) :: (load 4)
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G_STORE %2(s32), %0(p0) :: (store 4)
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%3(s16) = G_LOAD %0(p0) :: (load 2)
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G_STORE %3(s16), %0(p0) :: (store 2)
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%4(s8) = G_LOAD %0(p0) :: (load 1)
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G_STORE %4(s8), %0(p0) :: (store 1)
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%5(s1) = G_LOAD %0(p0) :: (load 1)
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G_STORE %5(s1), %0(p0) :: (store 1)
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%6(p0) = G_LOAD %0(p0) :: (load 4)
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G_STORE %6(p0), %0(p0) :: (store 4)
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BX_RET 14, $noreg
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...
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---
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name: test_load_from_stack
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# CHECK-LABEL: name: test_load_from_stack
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legalized: false
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# CHECK: legalized: true
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regBankSelected: false
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selected: false
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tracksRegLiveness: true
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registers:
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- { id: 0, class: _ }
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- { id: 1, class: _ }
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- { id: 2, class: _ }
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- { id: 3, class: _ }
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fixedStack:
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- { id: 0, offset: 0, size: 4, alignment: 4, isImmutable: true, isAliased: false }
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- { id: 1, offset: 4, size: 4, alignment: 4, isImmutable: true, isAliased: false }
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- { id: 2, offset: 8, size: 4, alignment: 4, isImmutable: true, isAliased: false }
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# CHECK: id: [[FRAME_INDEX:[0-9]+]], type: default, offset: 8
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body: |
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bb.0:
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liveins: $r0, $r1, $r2, $r3
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; This is legal, so we should find it unchanged in the output
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; CHECK: [[FIVREG:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.[[FRAME_INDEX]]
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; CHECK: {{%[0-9]+}}:_(s32) = G_LOAD [[FIVREG]](p0) :: (load 4)
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%0(p0) = G_FRAME_INDEX %fixed-stack.2
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%1(s32) = G_LOAD %0(p0) :: (load 4)
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$r0 = COPY %1(s32)
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BX_RET 14, $noreg, implicit $r0
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...
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---
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name: test_load_store_64_vfp
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# CHECK-LABEL: name: test_load_store_64_vfp
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legalized: false
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# CHECK: legalized: true
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regBankSelected: false
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selected: false
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tracksRegLiveness: true
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registers:
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- { id: 0, class: _ }
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- { id: 1, class: _ }
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- { id: 2, class: _ }
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body: |
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bb.0:
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liveins: $r0
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; Can't use the VFP support for unaligned operations, we need to use 32-bits
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; operations instead.
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; CHECK: [[ADDR1:%[0-9]+]]:_(p0) = COPY $r0
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; CHECK-NEXT: [[V1:%[0-9]+]]:_(s32) = G_LOAD [[ADDR1]](p0) :: (load 4, align 1)
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; CHECK-NEXT: [[OFF:%[0-9]+]]:_(s32) = G_CONSTANT i32 4
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; CHECK-NEXT: [[ADDR2:%[0-9]+]]:_(p0) = G_PTR_ADD [[ADDR1]], [[OFF]]
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; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY [[ADDR2]]
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; CHECK-NEXT: [[V2:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (load 4 + 4, align 1)
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; CHECK-NEXT: G_STORE [[V1]](s32), [[ADDR1]](p0) :: (store 4, align 1)
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; CHECK-NEXT: G_STORE [[V2]](s32), [[ADDR2]](p0) :: (store 4 + 4, align 1)
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%0(p0) = COPY $r0
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%1(s64) = G_LOAD %0(p0) :: (load 8, align 1)
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G_STORE %1(s64), %0(p0) :: (store 8, align 1)
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; For word-aligned we can use VFP operations.
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; CHECK: [[V:%[0-9]+]]:_(s64) = G_LOAD %0(p0) :: (load 8, align 4)
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; CHECK: G_STORE [[V]](s64), %0(p0) :: (store 8, align 4)
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%2(s64) = G_LOAD %0(p0) :: (load 8, align 4)
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G_STORE %2(s64), %0(p0) :: (store 8, align 4)
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BX_RET 14, $noreg
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...
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---
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name: test_load_store_64_novfp
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# CHECK-LABEL: name: test_load_store_64_novfp
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legalized: false
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# CHECK: legalized: true
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regBankSelected: false
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selected: false
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tracksRegLiveness: true
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registers:
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- { id: 0, class: _ }
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- { id: 1, class: _ }
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- { id: 2, class: _ }
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body: |
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bb.0:
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liveins: $r0
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; When we don't have VFP support, we need to use 32-bit operations.
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; CHECK: [[ADDR1:%[0-9]+]]:_(p0) = COPY $r0
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; CHECK-NEXT: [[V1:%[0-9]+]]:_(s32) = G_LOAD [[ADDR1]](p0) :: (load 4, align 1)
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; CHECK-NEXT: [[OFF:%[0-9]+]]:_(s32) = G_CONSTANT i32 4
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; CHECK-NEXT: [[ADDR2:%[0-9]+]]:_(p0) = G_PTR_ADD [[ADDR1]], [[OFF]]
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; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY [[ADDR2]]
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; CHECK-NEXT: [[V2:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (load 4 + 4, align 1)
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; CHECK-NEXT: G_STORE [[V1]](s32), [[ADDR1]](p0) :: (store 4, align 1)
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; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(p0) = COPY [[ADDR2]]
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; CHECK-NEXT: G_STORE [[V2]](s32), [[COPY2]](p0) :: (store 4 + 4, align 1)
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%0(p0) = COPY $r0
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%1(s64) = G_LOAD %0(p0) :: (load 8, align 1)
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G_STORE %1(s64), %0(p0) :: (store 8, align 1)
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; CHECK: [[V1:%[0-9]+]]:_(s32) = G_LOAD [[ADDR1]](p0) :: (load 4)
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; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(p0) = COPY [[ADDR2]]
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; CHECK-NEXT: [[V2:%[0-9]+]]:_(s32) = G_LOAD [[COPY3]](p0) :: (load 4 + 4)
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; CHECK-NEXT: G_STORE [[V1]](s32), [[ADDR1]](p0) :: (store 4)
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; CHECK-NEXT: G_STORE [[V2]](s32), [[ADDR2]](p0) :: (store 4 + 4)
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%2(s64) = G_LOAD %0(p0) :: (load 8, align 4)
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G_STORE %2(s64), %0(p0) :: (store 8, align 4)
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BX_RET 14, $noreg
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...
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---
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name: test_gep_s32
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# CHECK-LABEL: name: test_gep_s32
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legalized: false
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# CHECK: legalized: true
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regBankSelected: false
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selected: false
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tracksRegLiveness: true
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registers:
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- { id: 0, class: _ }
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- { id: 1, class: _ }
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- { id: 2, class: _ }
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body: |
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bb.0:
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liveins: $r0, $r1
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%0(p0) = COPY $r0
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%1(s32) = COPY $r1
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; CHECK: {{%[0-9]+}}:_(p0) = G_PTR_ADD {{%[0-9]+}}, {{%[0-9]+}}(s32)
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%2(p0) = G_PTR_ADD %0, %1(s32)
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$r0 = COPY %2(p0)
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BX_RET 14, $noreg, implicit $r0
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...
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---
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name: test_gep_s16
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# CHECK-LABEL: name: test_gep_s16
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legalized: false
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# CHECK: legalized: true
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regBankSelected: false
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selected: false
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tracksRegLiveness: true
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registers:
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- { id: 0, class: _ }
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- { id: 1, class: _ }
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- { id: 2, class: _ }
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body: |
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bb.0:
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liveins: $r0
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%0(p0) = COPY $r0
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%1(s16) = G_LOAD %0(p0) :: (load 2)
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; CHECK-NOT: G_PTR_ADD {{%[0-9]+}}, {{%[0-9]+}}(s16)
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; CHECK: {{%[0-9]+}}:_(p0) = G_PTR_ADD {{%[0-9]+}}, {{%[0-9]+}}(s32)
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; CHECK-NOT: G_PTR_ADD {{%[0-9]+}}, {{%[0-9]+}}(s16)
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%2(p0) = G_PTR_ADD %0, %1(s16)
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$r0 = COPY %2(p0)
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BX_RET 14, $noreg, implicit $r0
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...
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