Thomas Lively 92eadd3cde [WebAssembly][SIMD] Rename shuffle, swizzle, and load_splats ... These instructions previously used prefixes like v8x16 to signify that they were agnostic between float and int interpretations. We renamed these instructions to remove this form of prefix in https://github.com/WebAssembly/simd/issues/297 and https://github.com/WebAssembly/simd/issues/316 and this commit brings the names in LLVM up to date. Differential Revision: https://reviews.llvm.org/D93722		2020-12-22 14:29:06 -08:00
..
AArch64	[AArch64] Add support for the Branch Record Buffer extension	2020-12-18 11:11:06 +00:00
AMDGPU	[AMDGPU][MC][NFC] Lit tests cleanup	2020-12-21 20:04:02 +03:00
ARC
ARM
Hexagon
Lanai
Mips	[mips] Add tests to check disassembling of add.ps/mul.ps/sub.ps instructions	2020-11-13 14:31:12 +03:00
MSP430
PowerPC
RISCV	[RISCV] Add support for printing pcrel immediates as absolute addresses in llvm-objdump	2020-12-04 10:34:12 -08:00
Sparc
SystemZ
WebAssembly	[WebAssembly][SIMD] Rename shuffle, swizzle, and load_splats	2020-12-22 14:29:06 -08:00
X86	[X86] Teach assembler to accept vmsave/vmload/vmrun/invlpga/skinit with or without the fixed register operands	2020-12-19 11:01:55 -08:00
XCore