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c168815f4b
Summary: The -mcpu=mips16 option caused the Integrated Assembler to crash because it couldn't figure out the architecture revision number to write to the .MIPS.abiflags section. This CPU definition has been removed because, like microMIPS, MIPS16 is an ASE to a base architecture. Reviewers: vkalintiris Subscribers: rkotler, llvm-commits, dsanders Differential Revision: http://reviews.llvm.org/D13656 llvm-svn: 250407
91 lines
3.4 KiB
LLVM
91 lines
3.4 KiB
LLVM
; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16_h
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; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16_b
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@.str = private unnamed_addr constant [9 x i8] c"%hd %c \0A\00", align 1
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@sp = common global i16* null, align 4
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@cp = common global i8* null, align 4
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define void @p1(i16 signext %s, i8 signext %c) nounwind {
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entry:
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%conv = sext i16 %s to i32
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%conv1 = sext i8 %c to i32
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%call = tail call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([9 x i8], [9 x i8]* @.str, i32 0, i32 0), i32 %conv, i32 %conv1) nounwind
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ret void
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}
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declare i32 @printf(i8* nocapture, ...) nounwind
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define void @p2() nounwind {
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entry:
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%0 = load i16*, i16** @sp, align 4
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%1 = load i16, i16* %0, align 2
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%2 = load i8*, i8** @cp, align 4
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%3 = load i8, i8* %2, align 1
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%conv.i = sext i16 %1 to i32
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%conv1.i = sext i8 %3 to i32
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%call.i = tail call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([9 x i8], [9 x i8]* @.str, i32 0, i32 0), i32 %conv.i, i32 %conv1.i) nounwind
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%4 = load i16*, i16** @sp, align 4
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store i16 32, i16* %4, align 2
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%5 = load i8*, i8** @cp, align 4
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store i8 97, i8* %5, align 1
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ret void
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}
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define void @test() nounwind {
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entry:
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%s = alloca i16, align 4
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%c = alloca i8, align 4
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store i16 16, i16* %s, align 4
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store i8 99, i8* %c, align 4
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store i16* %s, i16** @sp, align 4
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store i8* %c, i8** @cp, align 4
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%call.i.i = call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([9 x i8], [9 x i8]* @.str, i32 0, i32 0), i32 16, i32 99) nounwind
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%0 = load i16*, i16** @sp, align 4
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store i16 32, i16* %0, align 2
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%1 = load i8*, i8** @cp, align 4
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store i8 97, i8* %1, align 1
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%2 = load i16, i16* %s, align 4
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%3 = load i8, i8* %c, align 4
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%conv.i = sext i16 %2 to i32
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%conv1.i = sext i8 %3 to i32
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%call.i = call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([9 x i8], [9 x i8]* @.str, i32 0, i32 0), i32 %conv.i, i32 %conv1.i) nounwind
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ret void
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; 16_b-LABEL: test:
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; 16_h-LABEL: test:
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; 16_b: sb ${{[0-9]+}}, [[offset1:[0-9]+]](${{[0-9]+}})
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; 16_b: lb ${{[0-9]+}}, [[offset1]](${{[0-9]+}})
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; 16_h: sh ${{[0-9]+}}, [[offset2:[0-9]+]](${{[0-9]+}})
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; 16_h: lh ${{[0-9]+}}, [[offset2]](${{[0-9]+}})
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}
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define i32 @main() nounwind {
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entry:
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%s.i = alloca i16, align 4
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%c.i = alloca i8, align 4
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%0 = bitcast i16* %s.i to i8*
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call void @llvm.lifetime.start(i64 -1, i8* %0) nounwind
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call void @llvm.lifetime.start(i64 -1, i8* %c.i) nounwind
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store i16 16, i16* %s.i, align 4
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store i8 99, i8* %c.i, align 4
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store i16* %s.i, i16** @sp, align 4
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store i8* %c.i, i8** @cp, align 4
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%call.i.i.i = call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([9 x i8], [9 x i8]* @.str, i32 0, i32 0), i32 16, i32 99) nounwind
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%1 = load i16*, i16** @sp, align 4
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store i16 32, i16* %1, align 2
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%2 = load i8*, i8** @cp, align 4
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store i8 97, i8* %2, align 1
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%3 = load i16, i16* %s.i, align 4
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%4 = load i8, i8* %c.i, align 4
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%conv.i.i = sext i16 %3 to i32
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%conv1.i.i = sext i8 %4 to i32
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%call.i.i = call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([9 x i8], [9 x i8]* @.str, i32 0, i32 0), i32 %conv.i.i, i32 %conv1.i.i) nounwind
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call void @llvm.lifetime.end(i64 -1, i8* %0) nounwind
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call void @llvm.lifetime.end(i64 -1, i8* %c.i) nounwind
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ret i32 0
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}
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declare void @llvm.lifetime.start(i64, i8* nocapture) nounwind
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declare void @llvm.lifetime.end(i64, i8* nocapture) nounwind
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