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ecad3cccfa
We should overall stop using these, but the uppercase name didn't work. Any feature string is converted to lowercase, so these could never be found in the table. llvm-svn: 357541
147 lines
4.4 KiB
TableGen
147 lines
4.4 KiB
TableGen
//===-- R600Processors.td - R600 Processor definitions --------------------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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class SubtargetFeatureFetchLimit <string Value> :
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SubtargetFeature <"fetch"#Value,
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"TexVTXClauseSize",
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Value,
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"Limit the maximum number of fetches in a clause to "#Value
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>;
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def FeatureR600ALUInst : SubtargetFeature<"R600ALUInst",
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"R600ALUInst",
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"false",
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"Older version of ALU instructions encoding"
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>;
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def FeatureFetchLimit8 : SubtargetFeatureFetchLimit <"8">;
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def FeatureFetchLimit16 : SubtargetFeatureFetchLimit <"16">;
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def FeatureVertexCache : SubtargetFeature<"HasVertexCache",
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"HasVertexCache",
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"true",
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"Specify use of dedicated vertex cache"
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>;
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def FeatureCaymanISA : SubtargetFeature<"caymanISA",
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"CaymanISA",
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"true",
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"Use Cayman ISA"
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>;
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def FeatureCFALUBug : SubtargetFeature<"cfalubug",
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"CFALUBug",
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"true",
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"GPU has CF_ALU bug"
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>;
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class R600SubtargetFeatureGeneration <string Value, string FeatureName,
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list<SubtargetFeature> Implies> :
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SubtargetFeatureGeneration <Value, FeatureName, "R600Subtarget", Implies>;
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def FeatureR600 : R600SubtargetFeatureGeneration<"R600", "r600",
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[FeatureR600ALUInst, FeatureFetchLimit8, FeatureLocalMemorySize0]
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>;
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def FeatureR700 : R600SubtargetFeatureGeneration<"R700", "r700",
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[FeatureFetchLimit16, FeatureLocalMemorySize0]
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>;
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def FeatureEvergreen : R600SubtargetFeatureGeneration<"EVERGREEN", "evergreen",
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[FeatureFetchLimit16, FeatureLocalMemorySize32768]
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>;
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def FeatureNorthernIslands : R600SubtargetFeatureGeneration<"NORTHERN_ISLANDS",
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"northern-islands",
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[FeatureFetchLimit16, FeatureWavefrontSize64,
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FeatureLocalMemorySize32768]
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>;
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//===----------------------------------------------------------------------===//
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// Radeon HD 2000/3000 Series (R600).
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//===----------------------------------------------------------------------===//
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def : Processor<"r600", R600_VLIW5_Itin,
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[FeatureR600, FeatureWavefrontSize64, FeatureVertexCache]
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>;
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def : Processor<"r630", R600_VLIW5_Itin,
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[FeatureR600, FeatureWavefrontSize32, FeatureVertexCache]
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>;
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def : Processor<"rs880", R600_VLIW5_Itin,
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[FeatureR600, FeatureWavefrontSize16]
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>;
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def : Processor<"rv670", R600_VLIW5_Itin,
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[FeatureR600, FeatureWavefrontSize64, FeatureVertexCache]
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>;
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//===----------------------------------------------------------------------===//
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// Radeon HD 4000 Series (R700).
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//===----------------------------------------------------------------------===//
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def : Processor<"rv710", R600_VLIW5_Itin,
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[FeatureR700, FeatureWavefrontSize32, FeatureVertexCache]
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>;
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def : Processor<"rv730", R600_VLIW5_Itin,
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[FeatureR700, FeatureWavefrontSize32, FeatureVertexCache]
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>;
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def : Processor<"rv770", R600_VLIW5_Itin,
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[FeatureR700, FeatureWavefrontSize64, FeatureVertexCache]
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>;
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//===----------------------------------------------------------------------===//
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// Radeon HD 5000 Series (Evergreen).
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//===----------------------------------------------------------------------===//
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def : Processor<"cedar", R600_VLIW5_Itin,
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[FeatureEvergreen, FeatureWavefrontSize32, FeatureVertexCache,
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FeatureCFALUBug]
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>;
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def : Processor<"cypress", R600_VLIW5_Itin,
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[FeatureEvergreen, FeatureWavefrontSize64, FeatureVertexCache, FeatureFMA]
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>;
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def : Processor<"juniper", R600_VLIW5_Itin,
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[FeatureEvergreen, FeatureWavefrontSize64, FeatureVertexCache]
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>;
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def : Processor<"redwood", R600_VLIW5_Itin,
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[FeatureEvergreen, FeatureWavefrontSize64, FeatureVertexCache,
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FeatureCFALUBug]
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>;
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def : Processor<"sumo", R600_VLIW5_Itin,
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[FeatureEvergreen, FeatureWavefrontSize64, FeatureCFALUBug]
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>;
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//===----------------------------------------------------------------------===//
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// Radeon HD 6000 Series (Northern Islands).
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//===----------------------------------------------------------------------===//
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def : Processor<"barts", R600_VLIW5_Itin,
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[FeatureNorthernIslands, FeatureVertexCache, FeatureCFALUBug]
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>;
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def : Processor<"caicos", R600_VLIW5_Itin,
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[FeatureNorthernIslands, FeatureCFALUBug]
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>;
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def : Processor<"cayman", R600_VLIW4_Itin,
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[FeatureNorthernIslands, FeatureCaymanISA, FeatureFMA]
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>;
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def : Processor<"turks", R600_VLIW5_Itin,
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[FeatureNorthernIslands, FeatureVertexCache, FeatureCFALUBug]
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>;
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