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llvm-mirror/test/MC/VE/DLD.s
Kazushi (Jam) Marukawa 04475a0f09 [VE] Support rest of load/store instructions in MC layer
Summary:
Add DLD/DLDU/DLDL/PFCH/TS1AM/TS2AM/TS3AM/ATMAM/CAS instructions newly.
Add regression tests for them to asmparser, mccodeemitter, and disassembler.
In order to add those instructions, change asmparser to support UImm0to2 and
UImm1 operands, add new decode functions to disassembler, and add new print
functions to instprinter.

Differential Revision: https://reviews.llvm.org/D81454
2020-06-09 14:21:00 +02:00

33 lines
1.1 KiB
ArmAsm

# RUN: llvm-mc -triple=ve --show-encoding < %s \
# RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
# RUN: llvm-mc -triple=ve -filetype=obj < %s | llvm-objdump -d - \
# RUN: | FileCheck %s --check-prefixes=CHECK-INST
# CHECK-INST: dld %s11, 8199
# CHECK-ENCODING: encoding: [0x07,0x20,0x00,0x00,0x00,0x00,0x0b,0x09]
dld %s11, 8199
# CHECK-INST: dld %s11, 20(%s11)
# CHECK-ENCODING: encoding: [0x14,0x00,0x00,0x00,0x00,0x8b,0x0b,0x09]
dld %s11, 20(%s11)
# CHECK-INST: dld %s11, -1(, %s11)
# CHECK-ENCODING: encoding: [0xff,0xff,0xff,0xff,0x8b,0x00,0x0b,0x09]
dld %s11, -1(, %s11)
# CHECK-INST: dld %s11, 20(%s10, %s11)
# CHECK-ENCODING: encoding: [0x14,0x00,0x00,0x00,0x8b,0x8a,0x0b,0x09]
dld %s11, 20(%s10, %s11)
# CHECK-INST: dldu %s11, 20(%s10, %s11)
# CHECK-ENCODING: encoding: [0x14,0x00,0x00,0x00,0x8b,0x8a,0x0b,0x0a]
dldu %s11, 20(%s10, %s11)
# CHECK-INST: dldl.sx %s11, 20(%s10, %s11)
# CHECK-ENCODING: encoding: [0x14,0x00,0x00,0x00,0x8b,0x8a,0x0b,0x0b]
dldl.sx %s11, 20(%s10, %s11)
# CHECK-INST: dldl.zx %s11, 20(%s10, %s11)
# CHECK-ENCODING: encoding: [0x14,0x00,0x00,0x00,0x8b,0x8a,0x8b,0x0b]
dldl.zx %s11, 20(%s10, %s11)