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llvm-mirror/test/MC/VE/NND.s
Kazushi (Jam) Marukawa e788281441 [VE] Support logical operation instructions in MC layer
Summary:
Add regression tests of asmparser, mccodeemitter, and disassembler for
logical operation instructions. Also change asmparser to support CMOV
instruction. And, add new EQV/MRG/NND isntructions also.

Differential Revision: https://reviews.llvm.org/D81219
2020-06-05 16:59:05 +02:00

29 lines
989 B
ArmAsm

# RUN: llvm-mc -triple=ve --show-encoding < %s \
# RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
# RUN: llvm-mc -triple=ve -filetype=obj < %s | llvm-objdump -d - \
# RUN: | FileCheck %s --check-prefixes=CHECK-INST
# CHECK-INST: nnd %s11, %s11, %s11
# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x00,0x8b,0x8b,0x0b,0x54]
nnd %s11, %s11, %s11
# CHECK-INST: nnd %s11, 63, %s11
# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x00,0x8b,0x3f,0x0b,0x54]
nnd %s11, 63, %s11
# CHECK-INST: nnd %s11, -1, %s11
# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x00,0x8b,0x7f,0x0b,0x54]
nnd %s11, -1, %s11
# CHECK-INST: nnd %s11, -64, %s11
# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x00,0x8b,0x40,0x0b,0x54]
nnd %s11, -64, %s11
# CHECK-INST: nnd %s11, -64, (32)1
# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x00,0x20,0x40,0x0b,0x54]
nnd %s11, -64, (32)1
# CHECK-INST: nnd %s11, 63, (32)0
# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x00,0x60,0x3f,0x0b,0x54]
nnd %s11, 63, (32)0