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463 lines
17 KiB
C++
463 lines
17 KiB
C++
//===- llvm/CodeGen/GlobalISel/InstructionSelector.h ------------*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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/// \file This file declares the API for the instruction selector.
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/// This class is responsible for selecting machine instructions.
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/// It's implemented by the target. It's used by the InstructionSelect pass.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_CODEGEN_GLOBALISEL_INSTRUCTIONSELECTOR_H
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#define LLVM_CODEGEN_GLOBALISEL_INSTRUCTIONSELECTOR_H
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#include "llvm/ADT/DenseMap.h"
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#include "llvm/ADT/Optional.h"
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#include "llvm/ADT/SmallVector.h"
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#include "llvm/Support/CodeGenCoverage.h"
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#include "llvm/Support/LowLevelTypeImpl.h"
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#include <bitset>
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#include <cstddef>
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#include <cstdint>
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#include <functional>
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#include <initializer_list>
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#include <vector>
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namespace llvm {
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class APInt;
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class APFloat;
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class MachineInstr;
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class MachineInstrBuilder;
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class MachineFunction;
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class MachineOperand;
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class MachineRegisterInfo;
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class RegisterBankInfo;
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class TargetInstrInfo;
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class TargetRegisterClass;
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class TargetRegisterInfo;
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/// Container class for CodeGen predicate results.
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/// This is convenient because std::bitset does not have a constructor
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/// with an initializer list of set bits.
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///
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/// Each InstructionSelector subclass should define a PredicateBitset class
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/// with:
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/// const unsigned MAX_SUBTARGET_PREDICATES = 192;
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/// using PredicateBitset = PredicateBitsetImpl<MAX_SUBTARGET_PREDICATES>;
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/// and updating the constant to suit the target. Tablegen provides a suitable
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/// definition for the predicates in use in <Target>GenGlobalISel.inc when
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/// GET_GLOBALISEL_PREDICATE_BITSET is defined.
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template <std::size_t MaxPredicates>
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class PredicateBitsetImpl : public std::bitset<MaxPredicates> {
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public:
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// Cannot inherit constructors because it's not supported by VC++..
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PredicateBitsetImpl() = default;
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PredicateBitsetImpl(const std::bitset<MaxPredicates> &B)
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: std::bitset<MaxPredicates>(B) {}
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PredicateBitsetImpl(std::initializer_list<unsigned> Init) {
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for (auto I : Init)
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std::bitset<MaxPredicates>::set(I);
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}
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};
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enum {
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/// Begin a try-block to attempt a match and jump to OnFail if it is
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/// unsuccessful.
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/// - OnFail - The MatchTable entry at which to resume if the match fails.
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///
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/// FIXME: This ought to take an argument indicating the number of try-blocks
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/// to exit on failure. It's usually one but the last match attempt of
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/// a block will need more. The (implemented) alternative is to tack a
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/// GIM_Reject on the end of each try-block which is simpler but
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/// requires an extra opcode and iteration in the interpreter on each
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/// failed match.
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GIM_Try,
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/// Switch over the opcode on the specified instruction
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/// - InsnID - Instruction ID
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/// - LowerBound - numerically minimum opcode supported
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/// - UpperBound - numerically maximum + 1 opcode supported
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/// - Default - failure jump target
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/// - JumpTable... - (UpperBound - LowerBound) (at least 2) jump targets
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GIM_SwitchOpcode,
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/// Switch over the LLT on the specified instruction operand
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/// - InsnID - Instruction ID
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/// - OpIdx - Operand index
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/// - LowerBound - numerically minimum Type ID supported
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/// - UpperBound - numerically maximum + 1 Type ID supported
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/// - Default - failure jump target
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/// - JumpTable... - (UpperBound - LowerBound) (at least 2) jump targets
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GIM_SwitchType,
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/// Record the specified instruction
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/// - NewInsnID - Instruction ID to define
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/// - InsnID - Instruction ID
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/// - OpIdx - Operand index
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GIM_RecordInsn,
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/// Check the feature bits
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/// - Expected features
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GIM_CheckFeatures,
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/// Check the opcode on the specified instruction
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/// - InsnID - Instruction ID
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/// - Expected opcode
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GIM_CheckOpcode,
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/// Check the instruction has the right number of operands
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/// - InsnID - Instruction ID
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/// - Expected number of operands
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GIM_CheckNumOperands,
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/// Check an immediate predicate on the specified instruction
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/// - InsnID - Instruction ID
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/// - The predicate to test
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GIM_CheckI64ImmPredicate,
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/// Check an immediate predicate on the specified instruction via an APInt.
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/// - InsnID - Instruction ID
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/// - The predicate to test
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GIM_CheckAPIntImmPredicate,
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/// Check a floating point immediate predicate on the specified instruction.
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/// - InsnID - Instruction ID
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/// - The predicate to test
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GIM_CheckAPFloatImmPredicate,
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/// Check a memory operation has the specified atomic ordering.
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/// - InsnID - Instruction ID
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/// - Ordering - The AtomicOrdering value
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GIM_CheckAtomicOrdering,
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GIM_CheckAtomicOrderingOrStrongerThan,
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GIM_CheckAtomicOrderingWeakerThan,
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/// Check the size of the memory access for the given machine memory operand.
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/// - InsnID - Instruction ID
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/// - MMOIdx - MMO index
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/// - Size - The size in bytes of the memory access
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GIM_CheckMemorySizeEqualTo,
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/// Check the size of the memory access for the given machine memory operand
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/// against the size of an operand.
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/// - InsnID - Instruction ID
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/// - MMOIdx - MMO index
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/// - OpIdx - The operand index to compare the MMO against
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GIM_CheckMemorySizeEqualToLLT,
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GIM_CheckMemorySizeLessThanLLT,
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GIM_CheckMemorySizeGreaterThanLLT,
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/// Check a generic C++ instruction predicate
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/// - InsnID - Instruction ID
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/// - PredicateID - The ID of the predicate function to call
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GIM_CheckCxxInsnPredicate,
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/// Check the type for the specified operand
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/// - InsnID - Instruction ID
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/// - OpIdx - Operand index
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/// - Expected type
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GIM_CheckType,
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/// Check the type of a pointer to any address space.
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/// - InsnID - Instruction ID
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/// - OpIdx - Operand index
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/// - SizeInBits - The size of the pointer value in bits.
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GIM_CheckPointerToAny,
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/// Check the register bank for the specified operand
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/// - InsnID - Instruction ID
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/// - OpIdx - Operand index
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/// - Expected register bank (specified as a register class)
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GIM_CheckRegBankForClass,
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/// Check the operand matches a complex predicate
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/// - InsnID - Instruction ID
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/// - OpIdx - Operand index
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/// - RendererID - The renderer to hold the result
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/// - Complex predicate ID
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GIM_CheckComplexPattern,
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/// Check the operand is a specific integer
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/// - InsnID - Instruction ID
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/// - OpIdx - Operand index
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/// - Expected integer
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GIM_CheckConstantInt,
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/// Check the operand is a specific literal integer (i.e. MO.isImm() or
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/// MO.isCImm() is true).
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/// - InsnID - Instruction ID
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/// - OpIdx - Operand index
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/// - Expected integer
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GIM_CheckLiteralInt,
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/// Check the operand is a specific intrinsic ID
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/// - InsnID - Instruction ID
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/// - OpIdx - Operand index
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/// - Expected Intrinsic ID
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GIM_CheckIntrinsicID,
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/// Check the specified operand is an MBB
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/// - InsnID - Instruction ID
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/// - OpIdx - Operand index
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GIM_CheckIsMBB,
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/// Check if the specified operand is safe to fold into the current
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/// instruction.
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/// - InsnID - Instruction ID
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GIM_CheckIsSafeToFold,
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/// Check the specified operands are identical.
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/// - InsnID - Instruction ID
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/// - OpIdx - Operand index
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/// - OtherInsnID - Other instruction ID
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/// - OtherOpIdx - Other operand index
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GIM_CheckIsSameOperand,
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/// Fail the current try-block, or completely fail to match if there is no
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/// current try-block.
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GIM_Reject,
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//=== Renderers ===
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/// Mutate an instruction
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/// - NewInsnID - Instruction ID to define
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/// - OldInsnID - Instruction ID to mutate
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/// - NewOpcode - The new opcode to use
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GIR_MutateOpcode,
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/// Build a new instruction
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/// - InsnID - Instruction ID to define
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/// - Opcode - The new opcode to use
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GIR_BuildMI,
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/// Copy an operand to the specified instruction
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/// - NewInsnID - Instruction ID to modify
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/// - OldInsnID - Instruction ID to copy from
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/// - OpIdx - The operand to copy
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GIR_Copy,
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/// Copy an operand to the specified instruction or add a zero register if the
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/// operand is a zero immediate.
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/// - NewInsnID - Instruction ID to modify
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/// - OldInsnID - Instruction ID to copy from
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/// - OpIdx - The operand to copy
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/// - ZeroReg - The zero register to use
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GIR_CopyOrAddZeroReg,
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/// Copy an operand to the specified instruction
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/// - NewInsnID - Instruction ID to modify
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/// - OldInsnID - Instruction ID to copy from
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/// - OpIdx - The operand to copy
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/// - SubRegIdx - The subregister to copy
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GIR_CopySubReg,
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/// Add an implicit register def to the specified instruction
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/// - InsnID - Instruction ID to modify
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/// - RegNum - The register to add
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GIR_AddImplicitDef,
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/// Add an implicit register use to the specified instruction
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/// - InsnID - Instruction ID to modify
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/// - RegNum - The register to add
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GIR_AddImplicitUse,
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/// Add an register to the specified instruction
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/// - InsnID - Instruction ID to modify
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/// - RegNum - The register to add
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GIR_AddRegister,
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/// Add a temporary register to the specified instruction
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/// - InsnID - Instruction ID to modify
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/// - TempRegID - The temporary register ID to add
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/// - TempRegFlags - The register flags to set
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GIR_AddTempRegister,
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/// Add an immediate to the specified instruction
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/// - InsnID - Instruction ID to modify
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/// - Imm - The immediate to add
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GIR_AddImm,
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/// Render complex operands to the specified instruction
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/// - InsnID - Instruction ID to modify
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/// - RendererID - The renderer to call
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GIR_ComplexRenderer,
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/// Render sub-operands of complex operands to the specified instruction
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/// - InsnID - Instruction ID to modify
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/// - RendererID - The renderer to call
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/// - RenderOpID - The suboperand to render.
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GIR_ComplexSubOperandRenderer,
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/// Render operands to the specified instruction using a custom function
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/// - InsnID - Instruction ID to modify
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/// - OldInsnID - Instruction ID to get the matched operand from
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/// - RendererFnID - Custom renderer function to call
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GIR_CustomRenderer,
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/// Render a G_CONSTANT operator as a sign-extended immediate.
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/// - NewInsnID - Instruction ID to modify
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/// - OldInsnID - Instruction ID to copy from
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/// The operand index is implicitly 1.
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GIR_CopyConstantAsSImm,
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/// Render a G_FCONSTANT operator as a sign-extended immediate.
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/// - NewInsnID - Instruction ID to modify
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/// - OldInsnID - Instruction ID to copy from
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/// The operand index is implicitly 1.
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GIR_CopyFConstantAsFPImm,
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/// Constrain an instruction operand to a register class.
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/// - InsnID - Instruction ID to modify
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/// - OpIdx - Operand index
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/// - RCEnum - Register class enumeration value
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GIR_ConstrainOperandRC,
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/// Constrain an instructions operands according to the instruction
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/// description.
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/// - InsnID - Instruction ID to modify
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GIR_ConstrainSelectedInstOperands,
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/// Merge all memory operands into instruction.
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/// - InsnID - Instruction ID to modify
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/// - MergeInsnID... - One or more Instruction ID to merge into the result.
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/// - GIU_MergeMemOperands_EndOfList - Terminates the list of instructions to
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/// merge.
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GIR_MergeMemOperands,
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/// Erase from parent.
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/// - InsnID - Instruction ID to erase
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GIR_EraseFromParent,
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/// Create a new temporary register that's not constrained.
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/// - TempRegID - The temporary register ID to initialize.
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/// - Expected type
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GIR_MakeTempReg,
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/// A successful emission
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GIR_Done,
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/// Increment the rule coverage counter.
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/// - RuleID - The ID of the rule that was covered.
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GIR_Coverage,
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/// Keeping track of the number of the GI opcodes. Must be the last entry.
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GIU_NumOpcodes,
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};
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enum {
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/// Indicates the end of the variable-length MergeInsnID list in a
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/// GIR_MergeMemOperands opcode.
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GIU_MergeMemOperands_EndOfList = -1,
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};
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/// Provides the logic to select generic machine instructions.
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class InstructionSelector {
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public:
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virtual ~InstructionSelector() = default;
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/// Select the (possibly generic) instruction \p I to only use target-specific
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/// opcodes. It is OK to insert multiple instructions, but they cannot be
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/// generic pre-isel instructions.
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///
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/// \returns whether selection succeeded.
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/// \pre I.getParent() && I.getParent()->getParent()
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/// \post
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/// if returns true:
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/// for I in all mutated/inserted instructions:
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/// !isPreISelGenericOpcode(I.getOpcode())
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virtual bool select(MachineInstr &I, CodeGenCoverage &CoverageInfo) const = 0;
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protected:
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using ComplexRendererFns =
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Optional<SmallVector<std::function<void(MachineInstrBuilder &)>, 4>>;
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using RecordedMIVector = SmallVector<MachineInstr *, 4>;
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using NewMIVector = SmallVector<MachineInstrBuilder, 4>;
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struct MatcherState {
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std::vector<ComplexRendererFns::value_type> Renderers;
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RecordedMIVector MIs;
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DenseMap<unsigned, unsigned> TempRegisters;
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MatcherState(unsigned MaxRenderers);
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};
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public:
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template <class PredicateBitset, class ComplexMatcherMemFn,
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class CustomRendererFn>
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struct ISelInfoTy {
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ISelInfoTy(const LLT *TypeObjects, size_t NumTypeObjects,
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const PredicateBitset *FeatureBitsets,
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const ComplexMatcherMemFn *ComplexPredicates,
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const CustomRendererFn *CustomRenderers)
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: TypeObjects(TypeObjects),
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FeatureBitsets(FeatureBitsets),
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ComplexPredicates(ComplexPredicates),
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CustomRenderers(CustomRenderers) {
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for (size_t I = 0; I < NumTypeObjects; ++I)
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TypeIDMap[TypeObjects[I]] = I;
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}
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const LLT *TypeObjects;
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const PredicateBitset *FeatureBitsets;
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const ComplexMatcherMemFn *ComplexPredicates;
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const CustomRendererFn *CustomRenderers;
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SmallDenseMap<LLT, unsigned, 64> TypeIDMap;
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};
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protected:
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InstructionSelector();
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/// Execute a given matcher table and return true if the match was successful
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/// and false otherwise.
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template <class TgtInstructionSelector, class PredicateBitset,
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class ComplexMatcherMemFn, class CustomRendererFn>
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bool executeMatchTable(
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TgtInstructionSelector &ISel, NewMIVector &OutMIs, MatcherState &State,
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const ISelInfoTy<PredicateBitset, ComplexMatcherMemFn, CustomRendererFn>
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&ISelInfo,
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const int64_t *MatchTable, const TargetInstrInfo &TII,
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MachineRegisterInfo &MRI, const TargetRegisterInfo &TRI,
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const RegisterBankInfo &RBI, const PredicateBitset &AvailableFeatures,
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CodeGenCoverage &CoverageInfo) const;
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virtual const int64_t *getMatchTable() const {
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llvm_unreachable("Should have been overridden by tablegen if used");
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}
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virtual bool testImmPredicate_I64(unsigned, int64_t) const {
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llvm_unreachable(
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"Subclasses must override this with a tablegen-erated function");
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}
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virtual bool testImmPredicate_APInt(unsigned, const APInt &) const {
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llvm_unreachable(
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"Subclasses must override this with a tablegen-erated function");
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}
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virtual bool testImmPredicate_APFloat(unsigned, const APFloat &) const {
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llvm_unreachable(
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"Subclasses must override this with a tablegen-erated function");
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}
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virtual bool testMIPredicate_MI(unsigned, const MachineInstr &) const {
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llvm_unreachable(
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"Subclasses must override this with a tablegen-erated function");
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}
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/// Constrain a register operand of an instruction \p I to a specified
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/// register class. This could involve inserting COPYs before (for uses) or
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/// after (for defs) and may replace the operand of \p I.
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/// \returns whether operand regclass constraining succeeded.
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bool constrainOperandRegToRegClass(MachineInstr &I, unsigned OpIdx,
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const TargetRegisterClass &RC,
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const TargetInstrInfo &TII,
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const TargetRegisterInfo &TRI,
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const RegisterBankInfo &RBI) const;
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bool isOperandImmEqual(const MachineOperand &MO, int64_t Value,
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const MachineRegisterInfo &MRI) const;
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/// Return true if the specified operand is a G_GEP with a G_CONSTANT on the
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/// right-hand side. GlobalISel's separation of pointer and integer types
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/// means that we don't need to worry about G_OR with equivalent semantics.
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bool isBaseWithConstantOffset(const MachineOperand &Root,
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const MachineRegisterInfo &MRI) const;
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/// Return true if MI can obviously be folded into IntoMI.
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/// MI and IntoMI do not need to be in the same basic blocks, but MI must
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/// preceed IntoMI.
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bool isObviouslySafeToFold(MachineInstr &MI, MachineInstr &IntoMI) const;
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};
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} // end namespace llvm
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#endif // LLVM_CODEGEN_GLOBALISEL_INSTRUCTIONSELECTOR_H
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