Nikolay Haustov 941b85256d [AMDGPU] Assembler: change v_madmk operands to have same order as mad. ... The constant is now at source operand 1 (previously at 2). This is also how it is in legacy AMD sp3 assembler. Update tests. Differential Revision: http://reviews.llvm.org/D17984 llvm-svn: 263212		2016-03-11 09:27:25 +00:00
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AArch64	AArch64: only try to use scaled fcvt ops on legal vector types.	2016-03-10 23:02:21 +00:00
AMDGPU	[AMDGPU] Assembler: change v_madmk operands to have same order as mad.	2016-03-11 09:27:25 +00:00
ARM	[ARM] Cortex-R8 support	2016-03-10 17:38:41 +00:00
BPF
CPP
Generic
Hexagon
Inputs
Mips	[mips][microMIPS] Prevent usage of OR16_MMR6 instruction when code for microMIPS is generated.	2016-03-04 17:34:31 +00:00
MIR	[MIR] Teach the parser/printer that generic virtual registers do not need a register class.	2016-03-08 01:17:03 +00:00
MSP430
NVPTX	[NVPTX] Use different, convergent MIs for convergent calls.	2016-03-01 19:24:03 +00:00
PowerPC	[PPC] backend changes to generate xvabs[s,d]p and xvnabs[s,d]p instructions	2016-03-09 17:48:01 +00:00
SPARC
SystemZ
Thumb
Thumb2	ARM: Introduce conservative load/store optimization mode	2016-03-02 19:20:00 +00:00
WebAssembly	[WebAssembly] Implement irreducible control flow.	2016-03-09 02:01:14 +00:00
WinEH	[WinEH] Make setjmp work correctly with EH	2016-02-29 19:16:03 +00:00
X86	[X86][SSE] Reapplied: Improve vector ZERO_EXTEND by combining to ZERO_EXTEND_VECTOR_INREG	2016-03-10 20:40:26 +00:00
XCore