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The new target machines are: nvptx (old ptx32) => 32-bit PTX nvptx64 (old ptx64) => 64-bit PTX The sources are based on the internal NVIDIA NVPTX back-end, and contain more functionality than the current PTX back-end currently provides. NV_CONTRIB llvm-svn: 156196
65 lines
1.5 KiB
LLVM
65 lines
1.5 KiB
LLVM
; RUN: llc < %s -march=nvptx -mcpu=sm_20 | FileCheck %s
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; RUN: llc < %s -march=nvptx64 -mcpu=sm_20 | FileCheck %s
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;; Integer conversions happen inplicitly by loading/storing the proper types
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; i16
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define i16 @cvt_i16_i32(i32 %x) {
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; CHECK: ld.param.u16 %rs[[R0:[0-9]+]], [cvt_i16_i32_param_{{[0-9]+}}]
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; CHECK: st.param.b16 [func_retval{{[0-9]+}}+0], %rs[[R0]]
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; CHECK: ret
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%a = trunc i32 %x to i16
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ret i16 %a
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}
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define i16 @cvt_i16_i64(i64 %x) {
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; CHECK: ld.param.u16 %rs[[R0:[0-9]+]], [cvt_i16_i64_param_{{[0-9]+}}]
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; CHECK: st.param.b16 [func_retval{{[0-9]+}}+0], %rs[[R0]]
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; CHECK: ret
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%a = trunc i64 %x to i16
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ret i16 %a
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}
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; i32
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define i32 @cvt_i32_i16(i16 %x) {
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; CHECK: ld.param.u16 %r[[R0:[0-9]+]], [cvt_i32_i16_param_{{[0-9]+}}]
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; CHECK: st.param.b32 [func_retval{{[0-9]+}}+0], %r[[R0]]
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; CHECK: ret
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%a = zext i16 %x to i32
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ret i32 %a
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}
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define i32 @cvt_i32_i64(i64 %x) {
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; CHECK: ld.param.u32 %r[[R0:[0-9]+]], [cvt_i32_i64_param_{{[0-9]+}}]
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; CHECK: st.param.b32 [func_retval{{[0-9]+}}+0], %r[[R0]]
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; CHECK: ret
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%a = trunc i64 %x to i32
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ret i32 %a
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}
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; i64
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define i64 @cvt_i64_i16(i16 %x) {
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; CHECK: ld.param.u16 %rl[[R0:[0-9]+]], [cvt_i64_i16_param_{{[0-9]+}}]
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; CHECK: st.param.b64 [func_retval{{[0-9]+}}+0], %rl[[R0]]
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; CHECK: ret
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%a = zext i16 %x to i64
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ret i64 %a
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}
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define i64 @cvt_i64_i32(i32 %x) {
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; CHECK: ld.param.u32 %rl[[R0:[0-9]+]], [cvt_i64_i32_param_{{[0-9]+}}]
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; CHECK: st.param.b64 [func_retval{{[0-9]+}}+0], %rl[[R0]]
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; CHECK: ret
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%a = zext i32 %x to i64
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ret i64 %a
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}
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