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https://github.com/RPCS3/llvm-mirror.git
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d09b64fc25
Adds an instruction itinerary to all x86 instructions, giving each a default latency of 1, using the InstrItinClass IIC_DEFAULT. Sets specific latencies for Atom for the instructions in files X86InstrCMovSetCC.td, X86InstrArithmetic.td, X86InstrControl.td, and X86InstrShiftRotate.td. The Atom latencies for the remainder of the x86 instructions will be set in subsequent patches. Adds a test to verify that the scheduler is working. Also changes the scheduling preference to "Hybrid" for i386 Atom, while leaving x86_64 as ILP. Patch by Preston Gurd! llvm-svn: 149558
77 lines
3.2 KiB
LLVM
77 lines
3.2 KiB
LLVM
; RUN: llc < %s -mcpu=generic -mtriple=x86_64-linux -asm-verbose=false | FileCheck %s
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; RUN: llc < %s -mcpu=generic -mtriple=x86_64-win32 -asm-verbose=false | FileCheck %s
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; LSR's OptimizeMax should eliminate the select (max).
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; CHECK: foo:
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; CHECK-NOT: cmov
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; CHECK: jle
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define void @foo(i64 %n, double* nocapture %p) nounwind {
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entry:
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%cmp6 = icmp slt i64 %n, 0 ; <i1> [#uses=1]
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br i1 %cmp6, label %for.end, label %for.body.preheader
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for.body.preheader: ; preds = %entry
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%tmp = icmp sgt i64 %n, 0 ; <i1> [#uses=1]
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%n.op = add i64 %n, 1 ; <i64> [#uses=1]
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%tmp1 = select i1 %tmp, i64 %n.op, i64 1 ; <i64> [#uses=1]
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br label %for.body
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for.body: ; preds = %for.body.preheader, %for.body
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%i = phi i64 [ %i.next, %for.body ], [ 0, %for.body.preheader ] ; <i64> [#uses=2]
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%arrayidx = getelementptr double* %p, i64 %i ; <double*> [#uses=2]
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%t4 = load double* %arrayidx ; <double> [#uses=1]
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%mul = fmul double %t4, 2.200000e+00 ; <double> [#uses=1]
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store double %mul, double* %arrayidx
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%i.next = add nsw i64 %i, 1 ; <i64> [#uses=2]
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%exitcond = icmp eq i64 %i.next, %tmp1 ; <i1> [#uses=1]
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br i1 %exitcond, label %for.end, label %for.body
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for.end: ; preds = %for.body, %entry
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ret void
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}
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; In this case, one of the max operands is another max, which folds,
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; leaving a two-operand max which doesn't fit the usual pattern.
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; OptimizeMax should handle this case.
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; PR7454
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; CHECK: _Z18GenerateStatusPagei:
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; CHECK: jle
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; CHECK-NOT: cmov
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; CHECK: xorl {{%edi, %edi|%ecx, %ecx|%eax, %eax}}
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; CHECK-NEXT: align
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; CHECK-NEXT: BB1_2:
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; CHECK: callq
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; CHECK-NEXT: incl [[BX:%[a-z0-9]+]]
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; CHECK-NEXT: cmpl [[R14:%[a-z0-9]+]], [[BX]]
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; CHECK: jl
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define void @_Z18GenerateStatusPagei(i32 %jobs_to_display) nounwind {
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entry:
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%cmp.i = icmp sgt i32 %jobs_to_display, 0 ; <i1> [#uses=1]
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%tmp = select i1 %cmp.i, i32 %jobs_to_display, i32 0 ; <i32> [#uses=3]
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%cmp8 = icmp sgt i32 %tmp, 0 ; <i1> [#uses=1]
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br i1 %cmp8, label %bb.nph, label %for.end
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bb.nph: ; preds = %entry
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%tmp11 = icmp sgt i32 %tmp, 1 ; <i1> [#uses=1]
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%smax = select i1 %tmp11, i32 %tmp, i32 1 ; <i32> [#uses=1]
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br label %for.body
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for.body: ; preds = %for.body, %bb.nph
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%i.010 = phi i32 [ 0, %bb.nph ], [ %inc, %for.body ] ; <i32> [#uses=1]
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%it.0.09 = phi float* [ null, %bb.nph ], [ %call.i, %for.body ] ; <float*> [#uses=1]
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%call.i = call float* @_ZSt18_Rb_tree_decrementPKSt18_Rb_tree_node_base(float* %it.0.09) ; <float*> [#uses=1]
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%inc = add nsw i32 %i.010, 1 ; <i32> [#uses=2]
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%exitcond = icmp eq i32 %inc, %smax ; <i1> [#uses=1]
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br i1 %exitcond, label %for.end, label %for.body
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for.end: ; preds = %for.body, %entry
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ret void
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}
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declare float* @_ZSt18_Rb_tree_decrementPKSt18_Rb_tree_node_base(float*)
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