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88025fac90
llvm-svn: 304954
231 lines
7.8 KiB
C++
231 lines
7.8 KiB
C++
//==- llvm/CodeGen/ExecutionDepsFix.h - Execution Dependency Fix -*- C++ -*-==//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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/// \file Execution Dependency Fix pass.
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///
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/// Some X86 SSE instructions like mov, and, or, xor are available in different
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/// variants for different operand types. These variant instructions are
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/// equivalent, but on Nehalem and newer cpus there is extra latency
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/// transferring data between integer and floating point domains. ARM cores
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/// have similar issues when they are configured with both VFP and NEON
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/// pipelines.
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///
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/// This pass changes the variant instructions to minimize domain crossings.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_CODEGEN_EXECUTIONDEPSFIX_H
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#define LLVM_CODEGEN_EXECUTIONDEPSFIX_H
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#include "llvm/ADT/DenseMap.h"
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#include "llvm/ADT/iterator_range.h"
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#include "llvm/ADT/SmallVector.h"
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#include "llvm/CodeGen/LivePhysRegs.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/RegisterClassInfo.h"
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#include "llvm/Pass.h"
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#include "llvm/Support/Allocator.h"
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#include "llvm/Support/MathExtras.h"
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#include <cassert>
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#include <limits>
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#include <utility>
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#include <vector>
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namespace llvm {
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class MachineBasicBlock;
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class MachineInstr;
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class TargetInstrInfo;
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/// A DomainValue is a bit like LiveIntervals' ValNo, but it also keeps track
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/// of execution domains.
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///
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/// An open DomainValue represents a set of instructions that can still switch
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/// execution domain. Multiple registers may refer to the same open
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/// DomainValue - they will eventually be collapsed to the same execution
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/// domain.
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///
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/// A collapsed DomainValue represents a single register that has been forced
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/// into one of more execution domains. There is a separate collapsed
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/// DomainValue for each register, but it may contain multiple execution
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/// domains. A register value is initially created in a single execution
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/// domain, but if we were forced to pay the penalty of a domain crossing, we
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/// keep track of the fact that the register is now available in multiple
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/// domains.
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struct DomainValue {
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// Basic reference counting.
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unsigned Refs = 0;
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// Bitmask of available domains. For an open DomainValue, it is the still
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// possible domains for collapsing. For a collapsed DomainValue it is the
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// domains where the register is available for free.
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unsigned AvailableDomains;
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// Pointer to the next DomainValue in a chain. When two DomainValues are
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// merged, Victim.Next is set to point to Victor, so old DomainValue
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// references can be updated by following the chain.
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DomainValue *Next;
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// Twiddleable instructions using or defining these registers.
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SmallVector<MachineInstr*, 8> Instrs;
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DomainValue() { clear(); }
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// A collapsed DomainValue has no instructions to twiddle - it simply keeps
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// track of the domains where the registers are already available.
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bool isCollapsed() const { return Instrs.empty(); }
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// Is domain available?
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bool hasDomain(unsigned domain) const {
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assert(domain <
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static_cast<unsigned>(std::numeric_limits<unsigned>::digits) &&
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"undefined behavior");
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return AvailableDomains & (1u << domain);
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}
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// Mark domain as available.
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void addDomain(unsigned domain) {
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AvailableDomains |= 1u << domain;
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}
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// Restrict to a single domain available.
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void setSingleDomain(unsigned domain) {
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AvailableDomains = 1u << domain;
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}
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// Return bitmask of domains that are available and in mask.
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unsigned getCommonDomains(unsigned mask) const {
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return AvailableDomains & mask;
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}
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// First domain available.
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unsigned getFirstDomain() const {
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return countTrailingZeros(AvailableDomains);
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}
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// Clear this DomainValue and point to next which has all its data.
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void clear() {
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AvailableDomains = 0;
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Next = nullptr;
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Instrs.clear();
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}
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};
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/// Information about a live register.
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struct LiveReg {
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/// Value currently in this register, or NULL when no value is being tracked.
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/// This counts as a DomainValue reference.
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DomainValue *Value;
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/// Instruction that defined this register, relative to the beginning of the
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/// current basic block. When a LiveReg is used to represent a live-out
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/// register, this value is relative to the end of the basic block, so it
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/// will be a negative number.
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int Def;
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};
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class ExecutionDepsFix : public MachineFunctionPass {
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SpecificBumpPtrAllocator<DomainValue> Allocator;
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SmallVector<DomainValue*,16> Avail;
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const TargetRegisterClass *const RC;
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MachineFunction *MF;
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const TargetInstrInfo *TII;
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const TargetRegisterInfo *TRI;
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RegisterClassInfo RegClassInfo;
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std::vector<SmallVector<int, 1>> AliasMap;
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const unsigned NumRegs;
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LiveReg *LiveRegs;
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struct MBBInfo {
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// Keeps clearance and domain information for all registers. Note that this
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// is different from the usual definition notion of liveness. The CPU
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// doesn't care whether or not we consider a register killed.
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LiveReg *OutRegs = nullptr;
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// Whether we have gotten to this block in primary processing yet.
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bool PrimaryCompleted = false;
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// The number of predecessors for which primary processing has completed
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unsigned IncomingProcessed = 0;
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// The value of `IncomingProcessed` at the start of primary processing
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unsigned PrimaryIncoming = 0;
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// The number of predecessors for which all processing steps are done.
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unsigned IncomingCompleted = 0;
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MBBInfo() = default;
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};
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using MBBInfoMap = DenseMap<MachineBasicBlock *, MBBInfo>;
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MBBInfoMap MBBInfos;
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/// List of undefined register reads in this block in forward order.
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std::vector<std::pair<MachineInstr *, unsigned>> UndefReads;
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/// Storage for register unit liveness.
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LivePhysRegs LiveRegSet;
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/// Current instruction number.
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/// The first instruction in each basic block is 0.
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int CurInstr;
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public:
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ExecutionDepsFix(char &PassID, const TargetRegisterClass &RC)
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: MachineFunctionPass(PassID), RC(&RC), NumRegs(RC.getNumRegs()) {}
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void getAnalysisUsage(AnalysisUsage &AU) const override {
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AU.setPreservesAll();
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MachineFunctionPass::getAnalysisUsage(AU);
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}
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bool runOnMachineFunction(MachineFunction &MF) override;
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MachineFunctionProperties getRequiredProperties() const override {
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return MachineFunctionProperties().set(
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MachineFunctionProperties::Property::NoVRegs);
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}
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private:
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iterator_range<SmallVectorImpl<int>::const_iterator>
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regIndices(unsigned Reg) const;
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// DomainValue allocation.
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DomainValue *alloc(int domain = -1);
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DomainValue *retain(DomainValue *DV) {
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if (DV) ++DV->Refs;
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return DV;
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}
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void release(DomainValue*);
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DomainValue *resolve(DomainValue*&);
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// LiveRegs manipulations.
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void setLiveReg(int rx, DomainValue *DV);
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void kill(int rx);
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void force(int rx, unsigned domain);
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void collapse(DomainValue *dv, unsigned domain);
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bool merge(DomainValue *A, DomainValue *B);
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void enterBasicBlock(MachineBasicBlock*);
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void leaveBasicBlock(MachineBasicBlock*);
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bool isBlockDone(MachineBasicBlock *);
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void processBasicBlock(MachineBasicBlock *MBB, bool PrimaryPass);
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bool visitInstr(MachineInstr *);
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void processDefs(MachineInstr *, bool breakDependency, bool Kill);
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void visitSoftInstr(MachineInstr*, unsigned mask);
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void visitHardInstr(MachineInstr*, unsigned domain);
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bool pickBestRegisterForUndef(MachineInstr *MI, unsigned OpIdx,
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unsigned Pref);
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bool shouldBreakDependence(MachineInstr*, unsigned OpIdx, unsigned Pref);
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void processUndefReads(MachineBasicBlock*);
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};
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} // end namepsace llvm
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#endif // LLVM_CODEGEN_EXECUTIONDEPSFIX_H
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