mirror of
https://github.com/RPCS3/llvm-mirror.git
synced 2024-10-25 22:12:57 +02:00
4e2def1840
TableGen had been nicely generating code to print a number of instructions using shorter aliases (and PowerPC has plenty of short mnemonics), but we were not calling it. For some of the aliases we support in the parser, TableGen can't infer the "inverse" alias relationship, so there is still more to do. Thus, after some hours of updating test cases... llvm-svn: 235616
535 lines
12 KiB
LLVM
535 lines
12 KiB
LLVM
; FIXME: FastISel currently returns false if it hits code that uses VSX
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; registers and with -fast-isel-abort=1 turned on the test case will then fail.
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; When fastisel better supports VSX fix up this test case.
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;
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; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 -mattr=-vsx | FileCheck %s --check-prefix=ELF64
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; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr8 -mattr=-vsx | FileCheck %s --check-prefix=ELF64LE
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; RUN: llc < %s -O0 -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -mcpu=970 -mattr=-vsx | FileCheck %s --check-prefix=PPC970
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;; Tests for 970 don't use -fast-isel-abort=1 because we intentionally punt
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;; to SelectionDAG in some cases.
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; Test sitofp
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define void @sitofp_single_i64(i64 %a, float %b) nounwind ssp {
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entry:
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; ELF64: sitofp_single_i64
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; ELF64LE: sitofp_single_i64
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; PPC970: sitofp_single_i64
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%b.addr = alloca float, align 4
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%conv = sitofp i64 %a to float
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; ELF64: std
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; ELF64: lfd
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; ELF64: fcfids
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; ELF64LE: std
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; ELF64LE: lfd
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; ELF64LE: fcfids
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; PPC970: std
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; PPC970: lfd
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; PPC970: fcfid
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; PPC970: frsp
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store float %conv, float* %b.addr, align 4
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ret void
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}
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define void @sitofp_single_i32(i32 %a, float %b) nounwind ssp {
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entry:
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; ELF64: sitofp_single_i32
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; ELF64LE: sitofp_single_i32
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; PPC970: sitofp_single_i32
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%b.addr = alloca float, align 4
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%conv = sitofp i32 %a to float
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; ELF64: std
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; stack offset used to load the float: 65524 = -16 + 4
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; ELF64: ori {{[0-9]+}}, {{[0-9]+}}, 65524
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; ELF64: lfiwax
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; ELF64: fcfids
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; ELF64LE: std
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; stack offset used to load the float: 65520 = -16 + 0
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; ELF64LE: ori {{[0-9]+}}, {{[0-9]+}}, 65520
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; ELF64LE: lfiwax
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; ELF64LE: fcfids
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; PPC970: std
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; PPC970: lfd
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; PPC970: fcfid
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; PPC970: frsp
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store float %conv, float* %b.addr, align 4
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ret void
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}
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define void @sitofp_single_i16(i16 %a, float %b) nounwind ssp {
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entry:
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; ELF64: sitofp_single_i16
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; ELF64LE: sitofp_single_i16
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; PPC970: sitofp_single_i16
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%b.addr = alloca float, align 4
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%conv = sitofp i16 %a to float
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; ELF64: extsh
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; ELF64: std
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; ELF64: lfd
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; ELF64: fcfids
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; ELF64LE: extsh
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; ELF64LE: std
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; ELF64LE: lfd
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; ELF64LE: fcfids
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; PPC970: extsh
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; PPC970: std
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; PPC970: lfd
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; PPC970: fcfid
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; PPC970: frsp
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store float %conv, float* %b.addr, align 4
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ret void
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}
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define void @sitofp_single_i8(i8 %a) nounwind ssp {
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entry:
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; ELF64: sitofp_single_i8
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; ELF64LE: sitofp_single_i8
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; PPC970: sitofp_single_i8
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%b.addr = alloca float, align 4
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%conv = sitofp i8 %a to float
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; ELF64: extsb
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; ELF64: std
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; ELF64: lfd
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; ELF64: fcfids
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; ELF64LE: extsb
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; ELF64LE: std
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; ELF64LE: lfd
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; ELF64LE: fcfids
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; PPC970: extsb
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; PPC970: std
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; PPC970: lfd
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; PPC970: fcfid
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; PPC970: frsp
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store float %conv, float* %b.addr, align 4
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ret void
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}
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define void @sitofp_double_i32(i32 %a, double %b) nounwind ssp {
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entry:
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; ELF64: sitofp_double_i32
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; ELF64LE: sitofp_double_i32
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; PPC970: sitofp_double_i32
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%b.addr = alloca double, align 8
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%conv = sitofp i32 %a to double
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; ELF64: std
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; stack offset used to load the float: 65524 = -16 + 4
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; ELF64: ori {{[0-9]+}}, {{[0-9]+}}, 65524
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; ELF64: lfiwax
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; ELF64: fcfid
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; ELF64LE: std
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; stack offset used to load the float: 65520 = -16 + 0
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; ELF64LE: ori {{[0-9]+}}, {{[0-9]+}}, 65520
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; ELF64LE: lfiwax
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; ELF64LE: fcfid
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; PPC970: std
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; PPC970: lfd
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; PPC970: fcfid
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store double %conv, double* %b.addr, align 8
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ret void
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}
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define void @sitofp_double_i64(i64 %a, double %b) nounwind ssp {
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entry:
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; ELF64: sitofp_double_i64
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; ELF64LE: sitofp_double_i64
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; PPC970: sitofp_double_i64
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%b.addr = alloca double, align 8
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%conv = sitofp i64 %a to double
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; ELF64: std
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; ELF64: lfd
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; ELF64: fcfid
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; ELF64LE: std
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; ELF64LE: lfd
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; ELF64LE: fcfid
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; PPC970: std
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; PPC970: lfd
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; PPC970: fcfid
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store double %conv, double* %b.addr, align 8
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ret void
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}
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define void @sitofp_double_i16(i16 %a, double %b) nounwind ssp {
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entry:
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; ELF64: sitofp_double_i16
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; ELF64LE: sitofp_double_i16
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; PPC970: sitofp_double_i16
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%b.addr = alloca double, align 8
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%conv = sitofp i16 %a to double
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; ELF64: extsh
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; ELF64: std
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; ELF64: lfd
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; ELF64: fcfid
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; ELF64LE: extsh
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; ELF64LE: std
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; ELF64LE: lfd
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; ELF64LE: fcfid
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; PPC970: extsh
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; PPC970: std
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; PPC970: lfd
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; PPC970: fcfid
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store double %conv, double* %b.addr, align 8
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ret void
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}
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define void @sitofp_double_i8(i8 %a, double %b) nounwind ssp {
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entry:
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; ELF64: sitofp_double_i8
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; ELF64LE: sitofp_double_i8
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; PPC970: sitofp_double_i8
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%b.addr = alloca double, align 8
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%conv = sitofp i8 %a to double
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; ELF64: extsb
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; ELF64: std
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; ELF64: lfd
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; ELF64: fcfid
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; ELF64LE: extsb
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; ELF64LE: std
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; ELF64LE: lfd
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; ELF64LE: fcfid
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; PPC970: extsb
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; PPC970: std
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; PPC970: lfd
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; PPC970: fcfid
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store double %conv, double* %b.addr, align 8
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ret void
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}
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; Test uitofp
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define void @uitofp_single_i64(i64 %a, float %b) nounwind ssp {
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entry:
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; ELF64: uitofp_single_i64
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; ELF64LE: uitofp_single_i64
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; PPC970: uitofp_single_i64
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%b.addr = alloca float, align 4
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%conv = uitofp i64 %a to float
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; ELF64: std
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; ELF64: lfd
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; ELF64: fcfidus
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; ELF64LE: std
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; ELF64LE: lfd
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; ELF64LE: fcfidus
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; PPC970-NOT: fcfidus
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store float %conv, float* %b.addr, align 4
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ret void
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}
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define void @uitofp_single_i32(i32 %a, float %b) nounwind ssp {
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entry:
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; ELF64: uitofp_single_i32
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; ELF64LE: uitofp_single_i32
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; PPC970: uitofp_single_i32
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%b.addr = alloca float, align 4
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%conv = uitofp i32 %a to float
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; ELF64: std
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; stack offset used to load the float: 65524 = -16 + 4
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; ELF64: ori {{[0-9]+}}, {{[0-9]+}}, 65524
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; ELF64: lfiwzx
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; ELF64: fcfidus
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; ELF64LE: std
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; stack offset used to load the float: 65520 = -16 + 0
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; ELF64LE: ori {{[0-9]+}}, {{[0-9]+}}, 65520
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; ELF64LE: lfiwzx
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; ELF64LE: fcfidus
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; PPC970-NOT: lfiwzx
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; PPC970-NOT: fcfidus
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store float %conv, float* %b.addr, align 4
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ret void
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}
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define void @uitofp_single_i16(i16 %a, float %b) nounwind ssp {
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entry:
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; ELF64: uitofp_single_i16
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; ELF64LE: uitofp_single_i16
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; PPC970: uitofp_single_i16
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%b.addr = alloca float, align 4
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%conv = uitofp i16 %a to float
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; ELF64: rldicl {{[0-9]+}}, {{[0-9]+}}, 0, 48
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; ELF64: std
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; ELF64: lfd
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; ELF64: fcfidus
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; ELF64LE: rldicl {{[0-9]+}}, {{[0-9]+}}, 0, 48
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; ELF64LE: std
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; ELF64LE: lfd
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; ELF64LE: fcfidus
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; PPC970: clrlwi {{[0-9]+}}, {{[0-9]+}}, 16
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; PPC970: std
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; PPC970: lfd
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; PPC970: fcfid
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; PPC970: frsp
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store float %conv, float* %b.addr, align 4
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ret void
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}
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define void @uitofp_single_i8(i8 %a) nounwind ssp {
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entry:
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; ELF64: uitofp_single_i8
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; ELF64LE: uitofp_single_i8
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; PPC970: uitofp_single_i8
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%b.addr = alloca float, align 4
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%conv = uitofp i8 %a to float
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; ELF64: rldicl {{[0-9]+}}, {{[0-9]+}}, 0, 56
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; ELF64: std
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; ELF64: lfd
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; ELF64: fcfidus
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; ELF64LE: rldicl {{[0-9]+}}, {{[0-9]+}}, 0, 56
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; ELF64LE: std
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; ELF64LE: lfd
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; ELF64LE: fcfidus
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; PPC970: clrlwi {{[0-9]+}}, {{[0-9]+}}, 24
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; PPC970: std
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; PPC970: lfd
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; PPC970: fcfid
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; PPC970: frsp
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store float %conv, float* %b.addr, align 4
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ret void
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}
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define void @uitofp_double_i64(i64 %a, double %b) nounwind ssp {
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entry:
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; ELF64: uitofp_double_i64
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; ELF64LE: uitofp_double_i64
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; PPC970: uitofp_double_i64
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%b.addr = alloca double, align 8
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%conv = uitofp i64 %a to double
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; ELF64: std
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; ELF64: lfd
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; ELF64: fcfidu
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; ELF64LE: std
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; ELF64LE: lfd
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; ELF64LE: fcfidu
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; PPC970-NOT: fcfidu
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store double %conv, double* %b.addr, align 8
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ret void
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}
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define void @uitofp_double_i32(i32 %a, double %b) nounwind ssp {
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entry:
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; ELF64: uitofp_double_i32
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; ELF64LE: uitofp_double_i32
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; PPC970: uitofp_double_i32
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%b.addr = alloca double, align 8
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%conv = uitofp i32 %a to double
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; ELF64: std
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; stack offset used to load the float: 65524 = -16 + 4
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; ELF64: ori {{[0-9]+}}, {{[0-9]+}}, 65524
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; ELF64: lfiwzx
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; ELF64: fcfidu
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; ELF64LE: std
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; stack offset used to load the float: 65520 = -16 + 0
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; ELF64LE: ori {{[0-9]+}}, {{[0-9]+}}, 65520
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; ELF64LE: lfiwzx
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; ELF64LE: fcfidu
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; PPC970-NOT: lfiwzx
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; PPC970-NOT: fcfidu
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store double %conv, double* %b.addr, align 8
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ret void
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}
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define void @uitofp_double_i16(i16 %a, double %b) nounwind ssp {
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entry:
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; ELF64: uitofp_double_i16
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; ELF64LE: uitofp_double_i16
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; PPC970: uitofp_double_i16
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%b.addr = alloca double, align 8
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%conv = uitofp i16 %a to double
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; ELF64: rldicl {{[0-9]+}}, {{[0-9]+}}, 0, 48
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; ELF64: std
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; ELF64: lfd
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; ELF64: fcfidu
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; ELF64LE: rldicl {{[0-9]+}}, {{[0-9]+}}, 0, 48
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; ELF64LE: std
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; ELF64LE: lfd
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; ELF64LE: fcfidu
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; PPC970: clrlwi {{[0-9]+}}, {{[0-9]+}}, 16
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; PPC970: std
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; PPC970: lfd
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; PPC970: fcfid
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store double %conv, double* %b.addr, align 8
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ret void
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}
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define void @uitofp_double_i8(i8 %a, double %b) nounwind ssp {
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entry:
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; ELF64: uitofp_double_i8
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; ELF64LE: uitofp_double_i8
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; PPC970: uitofp_double_i8
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%b.addr = alloca double, align 8
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%conv = uitofp i8 %a to double
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; ELF64: rldicl {{[0-9]+}}, {{[0-9]+}}, 0, 56
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; ELF64: std
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; ELF64: lfd
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; ELF64: fcfidu
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; ELF64LE: rldicl {{[0-9]+}}, {{[0-9]+}}, 0, 56
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; ELF64LE: std
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; ELF64LE: lfd
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; ELF64LE: fcfidu
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; PPC970: clrlwi {{[0-9]+}}, {{[0-9]+}}, 24
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; PPC970: std
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; PPC970: lfd
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; PPC970: fcfid
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store double %conv, double* %b.addr, align 8
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ret void
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}
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; Test fptosi
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define void @fptosi_float_i32(float %a) nounwind ssp {
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entry:
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; ELF64: fptosi_float_i32
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; ELF64LE: fptosi_float_i32
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; PPC970: fptosi_float_i32
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%b.addr = alloca i32, align 4
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%conv = fptosi float %a to i32
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; ELF64: fctiwz
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; ELF64: stfd
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; ELF64: lwa
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; ELF64LE: fctiwz
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; ELF64LE: stfd
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; ELF64LE: lwa
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; PPC970: fctiwz
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; PPC970: stfd
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; PPC970: lwa
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store i32 %conv, i32* %b.addr, align 4
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ret void
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}
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define void @fptosi_float_i64(float %a) nounwind ssp {
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entry:
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; ELF64: fptosi_float_i64
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; ELF64LE: fptosi_float_i64
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; PPC970: fptosi_float_i64
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%b.addr = alloca i64, align 4
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%conv = fptosi float %a to i64
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; ELF64: fctidz
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; ELF64: stfd
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; ELF64: ld
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; ELF64LE: fctidz
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; ELF64LE: stfd
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; ELF64LE: ld
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; PPC970: fctidz
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; PPC970: stfd
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; PPC970: ld
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store i64 %conv, i64* %b.addr, align 4
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ret void
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}
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define void @fptosi_double_i32(double %a) nounwind ssp {
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entry:
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; ELF64: fptosi_double_i32
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; ELF64LE: fptosi_double_i32
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; PPC970: fptosi_double_i32
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%b.addr = alloca i32, align 8
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%conv = fptosi double %a to i32
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; ELF64: fctiwz
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; ELF64: stfd
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; ELF64: lwa
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; ELF64LE: fctiwz
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; ELF64LE: stfd
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; ELF64LE: lwa
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; PPC970: fctiwz
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; PPC970: stfd
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; PPC970: lwa
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store i32 %conv, i32* %b.addr, align 8
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ret void
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}
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define void @fptosi_double_i64(double %a) nounwind ssp {
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entry:
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; ELF64: fptosi_double_i64
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; ELF64LE: fptosi_double_i64
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; PPC970: fptosi_double_i64
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%b.addr = alloca i64, align 8
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%conv = fptosi double %a to i64
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; ELF64: fctidz
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; ELF64: stfd
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; ELF64: ld
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; ELF64LE: fctidz
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; ELF64LE: stfd
|
|
; ELF64LE: ld
|
|
; PPC970: fctidz
|
|
; PPC970: stfd
|
|
; PPC970: ld
|
|
store i64 %conv, i64* %b.addr, align 8
|
|
ret void
|
|
}
|
|
|
|
; Test fptoui
|
|
|
|
define void @fptoui_float_i32(float %a) nounwind ssp {
|
|
entry:
|
|
; ELF64: fptoui_float_i32
|
|
; ELF64LE: fptoui_float_i32
|
|
; PPC970: fptoui_float_i32
|
|
%b.addr = alloca i32, align 4
|
|
%conv = fptoui float %a to i32
|
|
; ELF64: fctiwuz
|
|
; ELF64: stfd
|
|
; ELF64: lwz
|
|
; ELF64LE: fctiwuz
|
|
; ELF64LE: stfd
|
|
; ELF64LE: lwz
|
|
; PPC970: fctidz
|
|
; PPC970: stfd
|
|
; PPC970: lwz
|
|
store i32 %conv, i32* %b.addr, align 4
|
|
ret void
|
|
}
|
|
|
|
define void @fptoui_float_i64(float %a) nounwind ssp {
|
|
entry:
|
|
; ELF64: fptoui_float_i64
|
|
; ELF64LE: fptoui_float_i64
|
|
; PPC970: fptoui_float_i64
|
|
%b.addr = alloca i64, align 4
|
|
%conv = fptoui float %a to i64
|
|
; ELF64: fctiduz
|
|
; ELF64: stfd
|
|
; ELF64: ld
|
|
; ELF64LE: fctiduz
|
|
; ELF64LE: stfd
|
|
; ELF64LE: ld
|
|
; PPC970-NOT: fctiduz
|
|
store i64 %conv, i64* %b.addr, align 4
|
|
ret void
|
|
}
|
|
|
|
define void @fptoui_double_i32(double %a) nounwind ssp {
|
|
entry:
|
|
; ELF64: fptoui_double_i32
|
|
; ELF64LE: fptoui_double_i32
|
|
; PPC970: fptoui_double_i32
|
|
%b.addr = alloca i32, align 8
|
|
%conv = fptoui double %a to i32
|
|
; ELF64: fctiwuz
|
|
; ELF64: stfd
|
|
; ELF64: lwz
|
|
; ELF64LE: fctiwuz
|
|
; ELF64LE: stfd
|
|
; ELF64LE: lwz
|
|
; PPC970: fctidz
|
|
; PPC970: stfd
|
|
; PPC970: lwz
|
|
store i32 %conv, i32* %b.addr, align 8
|
|
ret void
|
|
}
|
|
|
|
define void @fptoui_double_i64(double %a) nounwind ssp {
|
|
entry:
|
|
; ELF64: fptoui_double_i64
|
|
; ELF64LE: fptoui_double_i64
|
|
; PPC970: fptoui_double_i64
|
|
%b.addr = alloca i64, align 8
|
|
%conv = fptoui double %a to i64
|
|
; ELF64: fctiduz
|
|
; ELF64: stfd
|
|
; ELF64: ld
|
|
; ELF64LE: fctiduz
|
|
; ELF64LE: stfd
|
|
; ELF64LE: ld
|
|
; PPC970-NOT: fctiduz
|
|
store i64 %conv, i64* %b.addr, align 8
|
|
ret void
|
|
}
|